Edge Effects on Gate Tunneling Current in HEMTs

2007 ◽  
Vol 54 (10) ◽  
pp. 2614-2622 ◽  
Author(s):  
D. Mahaveer Sathaiya ◽  
Shreepad Karmalkar
2012 ◽  
Vol 46 (3) ◽  
pp. 386-390 ◽  
Author(s):  
Iman Abaspur Kazerouni ◽  
Seyed Ebrahim Hosseini

2003 ◽  
Vol 50 (12) ◽  
pp. 2579-2581 ◽  
Author(s):  
Chang-Hoon Choi ◽  
Zhiping Yu ◽  
R.W. Dutton

2013 ◽  
Vol 772 ◽  
pp. 422-426
Author(s):  
Zhi Chao Zhao ◽  
Tie Feng Wu ◽  
Hui Bin Ma ◽  
Quan Wang ◽  
Jing Li

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel theory gate tunneling current predicting model using integral approach is presented in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using HSPICE simulator. The simulation results in BSIM4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.


2005 ◽  
Vol 26 (8) ◽  
pp. 550-552 ◽  
Author(s):  
J.C. Ranuarez ◽  
M.J. Deen ◽  
Chih-Hung Chen

2017 ◽  
Vol 12 (7) ◽  
pp. 724-730
Author(s):  
Zhao Zhichao ◽  
Wu Tiefeng ◽  
Li Jing ◽  
Wang Quan ◽  
Han Wanglong

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