Radiation-Induced Variable Retention Time in Dynamic Random Access Memories

Recently resistive random access memory (RRAM) is considered to be the most promising one to become the next generation memory since its simple Metal/Insulator/Metal (MIM) structure, lower power consumption and fabrication cost (Meena, J.S., et al., 2014. Overview of emerging nonvolatile memory technologies. Nanoscale Research Letters, 9(1), p.526). Due to some bottlenecks for current flash memory, such as high operation voltage, low operation speed, poor retention time and endurance, RRAM device is regarded as an alternative solution (Fuh, C.S., et al., 2011. Role of environmental and annealing conditions on the passivation-free In–Ga–Zn–O TFT. Thin Solid Films, 520, pp.1489–1494). In this investigation, the memory layer of RRAM device is IGZO, and it is deposited with AP-PECVD technique which can operate under atmosphere, reduce cost of the process. Microwave annealing (MWA) is used to enhance the RRAM device reliability (Fuh, C.S., et al., 2011. Role of environmental and annealing conditions on the passivation-free In–Ga–Zn–O TFT. Thin Solid Films, 520, pp.1489–1494). Experiment shows that with appropriate MWA treatment, the IGZO RRAM device exhibits better electrical characteristics, reliability issues such as numbers of switching cycle and data retention time are also improved (Teng, L.F., et al., 2012. Effects of microwave annealing on electrical enhancement of amorphous oxide semiconductor thin film transistor. Applied Physics Letters, 101, p.132901).

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The study of relation between variable retention time and channel implantation

Microelectronic Engineering ◽

10.1016/j.mee.2016.05.010 ◽

2016 ◽

Vol 162 ◽

pp. 82-84

Author(s):

Younghwan Son ◽

Myounggon Kang

Keyword(s):

Retention Time ◽

Variable Retention

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Nanoscale CuO solid-electrolyte-based conductive-bridging-random-access-memory cell operating multi-level-cell and 1selector1resistor

Journal of Materials Chemistry C ◽

10.1039/c5tc01342a ◽

2015 ◽

Vol 3 (37) ◽

pp. 9540-9550 ◽

Cited By ~ 12

Author(s):

Kyoung-Cheol Kwon ◽

Myung-Jin Song ◽

Ki-Hyun Kwon ◽

Han-Vit Jeoung ◽

Dong-Won Kim ◽

...

Keyword(s):

Solid Electrolyte ◽

Retention Time ◽

Random Access ◽

Memory Cell ◽

Random Access Memory ◽

Access Memory ◽

Multi Level

Nanoscale non-volatile CBRAM-cells are developed by using a CuO solid-electrolyte, providing a ∼102memory margin, ∼3 × 106endurance cycles, ∼6.63-years retention time at 85 °C, ∼100 ns writing speed, and MLC operation.

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One-Transistor Dynamic Random-Access Memory Based on Gate-All-Around Junction-Less Field-Effect Transistor with a Si/SiGe Heterostructure

Electronics ◽

10.3390/electronics9122134 ◽

2020 ◽

Vol 9 (12) ◽

pp. 2134

Author(s):

Young Jun Yoon ◽

Jae Sang Lee ◽

Dong-Seok Kim ◽

Sang Ho Lee ◽

In Man Kang

Keyword(s):

Quantum Well ◽

Retention Time ◽

Field Effect ◽

Field Effect Transistor ◽

Random Access ◽

Random Access Memory ◽

The Body ◽

Access Memory ◽

Effect Transistor ◽

Memory Applications

This paper presents a one-transistor dynamic random-access memory (1T-DRAM) cell based on a gate-all-around junction-less field-effect transistor (GAA-JLFET) with a Si/SiGe heterostructure for high-density memory applications. The proposed 1T-DRAM achieves the sensing margin using the difference in hole density in the body region between ‘1’ and ‘0’ states. The Si/SiGe heterostructure forms a quantum well in the body and reduces the band-to-band tunneling (BTBT) barrier between the body and drain. Compared with the performances of the 1T-DRAM with Si homo-structure, the proposed 1T-DRAM improves the sensing margin and retention time because its storage ability is enhanced by the quantum well. In addition, the thin BTBT barrier reduced the bias condition for the program operation. The proposed 1T-DRAM showed a high potential for memory applications by obtaining a high read current ratio at ‘1’ and ‘0’ states about 108 and a long retention time above 10 ms.

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A New Approach for Screening Retention Time Failure Bits in DRAM Device

ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2013p0403 ◽

2013 ◽

Author(s):

Bonggu Sung ◽

Daejung Kim ◽

Yongjik Park ◽

Joo-Sun Choi

Keyword(s):

Retention Time ◽

Random Access ◽

Random Access Memory ◽

Cell Plate ◽

Dynamic Random Access Memory ◽

Access Memory ◽

New Approach ◽

Root Cause ◽

Storage Node ◽

Node Voltage

Abstract In this paper, we investigate that Gate-Induced Drain Leakage (GIDL)-weak cells can be screened effectively by modulation of cell-plate voltage (VPlate) during retention time in dynamic random access memory (DRAM) with Negative Wordline bias scheme (NWL). Boosting storage-node voltage (VSP) by increase of VPlate is the root cause of generating additional GIDL fail bits.

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