Characterization of the Variable Retention Time in Dynamic Random Access Memory

2011 ◽  
Vol 58 (9) ◽  
pp. 2952-2958 ◽  
Author(s):  
Heesang Kim ◽  
Byoungchan Oh ◽  
Younghwan Son ◽  
Kyungdo Kim ◽  
Seon-Yong Cha ◽  
...  
Keyword(s):  
Retention Time ◽  
Random Access ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Variable Retention

Reliability and Characterization of Composite Oxide/Nitride Dielectrics for Multi‐Megabit Dynamic Random Access Memory Stacked Capacitors

1991 ◽  
Vol 138 (7) ◽  
pp. 2052-2057 ◽  
Author(s):  
P. C. Fazan ◽  
A. Ditali ◽  
C. H. Dennison ◽  
H. E. Rhodes ◽  
H. C. Chan ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Composite Oxide

A New Approach for Screening Retention Time Failure Bits in DRAM Device

2013 ◽  
Author(s):  
Bonggu Sung ◽  
Daejung Kim ◽  
Yongjik Park ◽  
Joo-Sun Choi
Keyword(s):  
Retention Time ◽  
Random Access ◽  
Random Access Memory ◽  
Cell Plate ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
New Approach ◽  
Root Cause ◽  
Storage Node ◽  
Node Voltage

Abstract In this paper, we investigate that Gate-Induced Drain Leakage (GIDL)-weak cells can be screened effectively by modulation of cell-plate voltage (VPlate) during retention time in dynamic random access memory (DRAM) with Negative Wordline bias scheme (NWL). Boosting storage-node voltage (VSP) by increase of VPlate is the root cause of generating additional GIDL fail bits.

Deposition and Electrical Characterization of Very ThinSrTiO3Films for Ultra Large Scale Integrated Dynamic Random Access Memory Application

1995 ◽  
Vol 34 (Part 1, No. 9B) ◽  
pp. 5178-5183 ◽  
Author(s):  
Cheol Seong Hwang ◽  
Soon Oh Park ◽  
Chang Seok Kang ◽  
Hag-Ju Cho ◽  
Ho-Kyu Kang ◽  
...  
Keyword(s):  
Large Scale ◽  
Random Access ◽  
Electrical Characterization ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory

scholarly journals Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM

Micromachines ◽  
2020 ◽  
Vol 11 (11) ◽  
pp. 952
Author(s):  
Songyi Yoo ◽  
Wookyung Sun ◽  
Hyungsoon Shin
Keyword(s):  
Retention Time ◽  
Computer Aided Design ◽  
Memory Performance ◽  
Scaling Limit ◽  
Random Access ◽  
Random Access Memory ◽  
Memory Device ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Aided Design

A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.

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