A New Approach for Screening Retention Time Failure Bits in DRAM Device
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Abstract In this paper, we investigate that Gate-Induced Drain Leakage (GIDL)-weak cells can be screened effectively by modulation of cell-plate voltage (VPlate) during retention time in dynamic random access memory (DRAM) with Negative Wordline bias scheme (NWL). Boosting storage-node voltage (VSP) by increase of VPlate is the root cause of generating additional GIDL fail bits.
1998 ◽
Vol 45
(6)
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pp. 1300-1309
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2011 ◽
Vol 58
(9)
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pp. 2952-2958
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2002 ◽
Vol 41
(Part 1, No. 12)
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pp. 7276-7281
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