Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery

A method for determining adequate quantities and locations of on-chip capacitors to maintain supply voltages at all locations on a chip within pre-specified limits given the switching activity of on-chip circuits was presented in [3]. In this paper, we extend the method to include current flow from the package and PCB. The effects of on-chip capacitance and other system parasitics on the time it takes for additional supply current to flow into a chip are discussed. The relationship between switching current, capacitance, system parasitic inductances, and on-chip noise is presented. These concepts are then applied to the subject of power delivery network (PDN) resonance. A 1-dimensional model for simulating PDN resonance is presented. The model includes chip, package, and PCB components, along with explicit networks for each chip power supply and their interactions. The topology of the model and the contributions of each model component are described. A design methodology for avoiding PDN resonance, presently in use on all IBM ASIC modules, is presented.

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A Load Balanced Charging Strategy for Electric Vehicle in Smart Grid

Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering - Smart Grid Inspired Future Technologies ◽

10.1007/978-3-319-47729-9_16 ◽

2016 ◽

pp. 155-164 ◽

Cited By ~ 1

Author(s):

Qiang Tang ◽

Ming-zhong Xie ◽

Li Wang ◽

Yuan-sheng Luo ◽

Kun Yang

Keyword(s):

Smart Grid ◽

Electric Vehicle ◽

Charging Strategy ◽

Load Balanced

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Analysis of on chip decoupling capacitor in the double-gate FinFETs with PEEC-based power delivery network

2014 International SoC Design Conference (ISOCC) ◽

10.1109/isocc.2014.7087653 ◽

2014 ◽

Author(s):

Jaemin Lee ◽

Yesung Kang ◽

Youngmin Kim

Keyword(s):

Power Delivery ◽

Double Gate ◽

Power Delivery Network ◽

Decoupling Capacitor ◽

On Chip ◽

Delivery Network

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A Sub-THz Wireless Power Transfer for Non-Contact Wafer-Level Testing

Electronics ◽

10.3390/electronics9081210 ◽

2020 ◽

Vol 9 (8) ◽

pp. 1210

Author(s):

Hanh Dang-ba ◽

Gyung-su Byun

Keyword(s):

Wireless Power Transfer ◽

Cmos Technology ◽

Power Delivery ◽

Transfer Efficiency ◽

Power Transfer ◽

Wireless Power ◽

Wafer Level ◽

Power Transfer Efficiency ◽

Chip Size ◽

On Chip

In this paper, a sub-THz wireless power transfer (WPT) interface for non-contact wafer-level testing is proposed. The on-chip sub-THz couplers, which have been designed and analyzed with 3-D EM simulations, could be integrated into the WPT to transfer power through an air media. By using the sub-THz coils, the WPT occupies an extremely small chip size, which is suitable for future wafer-testing applications. In the best power transfer efficiency (PTE) condition of the WPT, the maximum power delivery is limited to 2.5 mW per channel. However, multi-channel sub-THz WPT could be a good solution to provide enough power for testing purposes while remaining high PTE. Simulated on a standard 28-nm CMOS technology, the proposed eight-channel WPT could provide 20 mW power with the PTE of 16%. The layouts of the eight-channel WPT transmitter and receiver occupy only 0.12 mm2, 0.098 mm2, respectively.

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Deadlock Free Load Balanced Adaptive Routing for Network on Chip (NoC) Systems

Journal of Computational and Theoretical Nanoscience ◽

10.1166/jctn.2016.5757 ◽

2016 ◽

Vol 13 (10) ◽

pp. 7592-7598

Author(s):

J Kalaivani ◽

B Vinayagasundaram

Keyword(s):

Packet Loss ◽

Probability Function ◽

Adaptive Routing ◽

Network On Chip ◽

Communication Architecture ◽

Data Packets ◽

Oblivious Routing ◽

Simulation Results ◽

On Chip ◽

Load Balanced

The Network-on-Chip (NoC) systems have emerged in on-chip communication architecture in various fields. To achieve excellent results in Network on Chip (NoC) systems application, the routing must eliminate the deadlock issues from the network. To overcome this issue in the network, in this paper, we propose Deadlock Free Load Balanced Adaptive Routing. In this approach, Oblivious Routing (OR) algorithm is implemented on the channel by using the probability function. The network considers the capacity of the node and tries to maximize the throughput based on the connectivity between the data packets flow and minimize the channel load. A Reconfiguration Protocol is used for the data packets to choose other channel in the network if the deadlock occurs. Simulation results show that this approach reduces the delay and packet loss in the network.

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