Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery

2005 ◽  
Author(s):  
Zhenyu Qi ◽  
Hang Li ◽  
S.X.-D. Tan ◽  
Lifeng Wu ◽  
Yici Cai ◽  
...  
Keyword(s):  
Power Delivery ◽  
Allocation Algorithm ◽  
On Chip

Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery

2017 ◽  
Vol 25 (9) ◽  
pp. 2538-2551 ◽  
Author(s):  
Divya Pathak ◽  
Houman Homayoun ◽  
Ioannis Savidis
Keyword(s):  
Smart Grid ◽  
Work Load ◽  
Power Delivery ◽  
On Chip ◽  
Load Balanced

PCB Effects on On-chip Capacitor Requirements and an Efficient Resonance-Prevention ASIC Methodology

2010 ◽  
Vol 2010 (1) ◽  
pp. 000392-000399
Author(s):  
Timothy Budell ◽  
Eric Tremble
Keyword(s):  
Design Methodology ◽  
Current Flow ◽  
Power Delivery ◽  
Switching Activity ◽  
Dimensional Model ◽  
Power Delivery Network ◽  
Model Component ◽  
The Subject ◽  
On Chip ◽  
The Relationship

A method for determining adequate quantities and locations of on-chip capacitors to maintain supply voltages at all locations on a chip within pre-specified limits given the switching activity of on-chip circuits was presented in [3]. In this paper, we extend the method to include current flow from the package and PCB. The effects of on-chip capacitance and other system parasitics on the time it takes for additional supply current to flow into a chip are discussed. The relationship between switching current, capacitance, system parasitic inductances, and on-chip noise is presented. These concepts are then applied to the subject of power delivery network (PDN) resonance. A 1-dimensional model for simulating PDN resonance is presented. The model includes chip, package, and PCB components, along with explicit networks for each chip power supply and their interactions. The topology of the model and the contributions of each model component are described. A design methodology for avoiding PDN resonance, presently in use on all IBM ASIC modules, is presented.

scholarly journals A Sub-THz Wireless Power Transfer for Non-Contact Wafer-Level Testing

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1210
Author(s):  
Hanh Dang-ba ◽  
Gyung-su Byun
Keyword(s):  
Wireless Power Transfer ◽  
Cmos Technology ◽  
Power Delivery ◽  
Transfer Efficiency ◽  
Power Transfer ◽  
Wireless Power ◽  
Wafer Level ◽  
Power Transfer Efficiency ◽  
Chip Size ◽  
On Chip

In this paper, a sub-THz wireless power transfer (WPT) interface for non-contact wafer-level testing is proposed. The on-chip sub-THz couplers, which have been designed and analyzed with 3-D EM simulations, could be integrated into the WPT to transfer power through an air media. By using the sub-THz coils, the WPT occupies an extremely small chip size, which is suitable for future wafer-testing applications. In the best power transfer efficiency (PTE) condition of the WPT, the maximum power delivery is limited to 2.5 mW per channel. However, multi-channel sub-THz WPT could be a good solution to provide enough power for testing purposes while remaining high PTE. Simulated on a standard 28-nm CMOS technology, the proposed eight-channel WPT could provide 20 mW power with the PTE of 16%. The layouts of the eight-channel WPT transmitter and receiver occupy only 0.12 mm2, 0.098 mm2, respectively.

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