Sheet carrier concentration and threshold voltage modeling of asymmetrically doped AlGaN/GaN/AlGaN double heterostructure HEMT

2017 ◽  
Author(s):  
Nisha Chugh ◽  
Monika Bhattacharya ◽  
Manoj Kumar ◽  
R.S Gupta
Keyword(s):  
Carrier Concentration ◽  
Threshold Voltage ◽  
Double Heterostructure

Comparison of 4H-SiC MOSFETs on (0001), (000-1) and (11-20) Oriented Substrates

2009 ◽  
Vol 615-617 ◽  
pp. 785-788 ◽  
Author(s):  
Harsh Naik ◽  
K. Tang ◽  
T. Marron ◽  
T. Paul Chow ◽  
Jody Fronheiser
Keyword(s):  
Low Temperature ◽  
Carrier Concentration ◽  
Threshold Voltage ◽  
Hall Mobility ◽  
Field Effect ◽  
Gate Oxide ◽  
Subthreshold Slope ◽  
Field Effect Mobility

The effect of using different orientations of 4H-SiC substrates on the performance of 4H-SiC MOSFETs has been evaluated. Three sets of samples with (0001), (000-1) and (11-20) oriented SiC substrates were used to fabricate the MOSFETs, with a gate oxide process consisting of a low- temperature deposited oxide followed by NO anneal at 1175°C for 2hrs. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted. Temperature characterization up to 225°C was also performed.

Effect of Graphite Cap for Implant Activation on Inversion Channel Mobility in 4H-SiC MOSFETs

2009 ◽  
Vol 615-617 ◽  
pp. 773-776 ◽  
Author(s):  
Harsh Naik ◽  
K. Tang ◽  
T. Paul Chow
Keyword(s):  
Low Temperature ◽  
Carrier Concentration ◽  
Threshold Voltage ◽  
Hall Mobility ◽  
Field Effect ◽  
Gate Oxide ◽  
Subthreshold Slope ◽  
Field Effect Mobility ◽  
Channel Mobility ◽  
Inversion Channel

The effects of using a graphite capping layer during implant activation anneal on the performance of 4H-SiC MOSFETs has been evaluated. Two sets of samples, one with the graphite cap and another without, with a gate oxide process consisting of a low-temperature deposited oxide followed by NO anneal at 1175°C for 2hrs were used for characterization. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted for the two processes.

Carrier Concentration and Threshold Voltage Variability of Amorphous Oxide Semiconductors Using Vacuum Rapid Thermal Annealing

2020 ◽  
Vol 20 (7) ◽  
pp. 4276-4281
Author(s):  
Joong-Won Shin ◽  
Won-Ju Cho
Keyword(s):  
Thin Films ◽  
Binding Energy ◽  
Carrier Concentration ◽  
Leakage Current ◽  
Rapid Thermal Annealing ◽  
Electron Concentration ◽  
Threshold Voltage ◽  
Lattice Oxygen ◽  
Zno Films ◽  
Oxide Semiconductors

This study evaluates the effect of rapid thermal annealing (RTA) in vacuum on the electrical properties of various amorphous oxide semiconductors (AOSs). We fabricated bottom-gate type TFTs using four types of a-IGZO (In2O3:Ga2O3:ZnO = 1:1:1, 1:1:2, 4:2:3, 4:2:4.1), a-ZTO (ZnO:SnO2 = 1:1), a-ZnO, or two types of a-AZTO (Al2O3:ZnO:SnO2 = 3:67:30, 2:10:10) thin films on the active channel and performed vacuum RTA at various temperatures. Measurement of the electrical characteristics of the thin film transistors (TFTs) revealed a unique behavior that the on-current of a-IGZO and a-ZnO TFTs increases with increasing vacuum RTA temperature, while threshold voltage (VTH) shifts significantly in the negative direction and increases the leakage current. As a result of analyzing the resistivity and carrier concentration of the AOS thin films using the Hall measurement, it was verified that the electron concentration increases as the vacuum RTA temperature increases, resulting in a decrease in resistivity. In addition, the increase in the carrier concentration of the IGZO and ZnO films is larger than that of the ZTO and AZTO films. In particular, the IGZO film with a composition of 4:2:3 showed the largest electron increase, while the AZTO film with a composition of 2:10:10 showed the smallest electron increase. XPS analysis has demonstrated that a reduction in lattice oxygen concentration is observed in vacuum RTA-processed AOS thin films. The reduction of lattice oxygen in the IGZO film of 4:2:3 was the largest, but in AZTO film 2:10:10 was the smallest. The reduction of lattice oxygen due to vacuum RTA results in an increase in oxygen vacancies, resulting in an increase in electron concentration, an increase in on-current, a negative shift in VTH, and an increase in leakage current. The loss of lattice oxygen in AOS thin films depends on the metal-oxygen binding energy. Since Al and Sn in the ZTO and AZTO films have a large binding energy with oxygen, the oxygen hardly diffuses out of the film and little change in VTH occurs. In comparison, the binding energy of In, Ga, and Zn of IGZO and ZnO films are small. Therefore, the higher the external diffusion of oxygen in IGZO and ZnO films by vacuum RTA, the variability of the carrier concentration and the VTH become larger.

The III-Nitride Double Heterostructure Revisited: Benefits for Threshold Voltage Engineering of MIS Devices

2016 ◽  
Vol 63 (2) ◽  
pp. 606-613 ◽  
Author(s):  
Herwig Hahn ◽  
Carsten Funck ◽  
Sascha Geipel ◽  
Holger Kalisch ◽  
Andrei Vescan
Keyword(s):  
Threshold Voltage ◽  
Double Heterostructure ◽  
Mis Devices

SiC and GaN MOS Interfaces – Similarities and Differences

2010 ◽  
Vol 645-648 ◽  
pp. 473-478 ◽  
Author(s):  
T. Paul Chow
Keyword(s):  
Carrier Concentration ◽  
Threshold Voltage ◽  
Field Effect ◽  
Gate Oxide ◽  
Electron Trapping ◽  
Electrical Characteristics ◽  
Subthreshold Slope ◽  
Field Effect Mobility ◽  
Mos Capacitors ◽  
Similarities And Differences

We have comparatively characterized the electrical characteristics of 4H-SiC and 2H-GaN MOS capacitors and FETs. While progressive refinement of gate oxide processes, notably with NO anneal, has resulted in better threshold voltage control, reduced subthreshold slope and higher field-effect mobility for 4H-SiC MOSFETs, we have recently reported more superior MOS parameters for 2H-GaN MOSFETs. In addition, we have performed MOS-gated Hall measurements to extract the intrinsic carrier concentration and MOS mobility, indicating that both less channel electron trapping and scattering take place in 2H-GaN MOSFETs.

Bias Stress Stability of Asymmetric Source-Drain a-Si:H Thin Film Transistors

2006 ◽  
Vol 910 ◽  
Author(s):  
Kwang-Sub Shin ◽  
Jae-Hoon Lee ◽  
Won-kyu Lee ◽  
Sang-Geun Park ◽  
Min-Koo Han
Keyword(s):  
Thin Film ◽  
Carrier Concentration ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Bias Stress ◽  
Electrical Stress ◽  
Defect Creation ◽  
Drain Bias ◽  
Charge Depletion

AbstractThe threshold voltage (VT) degradation of asymmetric source-drain a-Si:H TFTs due to the electrical stress has been investigated. In the absence of a drain bias (VG=15V, VD=0V), the threshold voltage (VT) shifts of asymmetric TFTs were similar to that of symmetric TFT. However, in the presence of drain bias (VG=15V, VD=20V), the VT shifts of asymmetric TFTs were less than symmetric TFT. The VT shifts of ‘L’ and ‘J’ shaped TFT were 0.29V, 0.24V respectively, while the VT shift of ‘I’ shaped TFT was 0.42V.The less VT degradation of the asymmetric source-drain a-Si:H TFT compared with the symmetric TFT may be explained by the defect creation model. Since the actual drain width of asymmetric TFT is longer than symmetric TFT at the same W/L ratio, the charge depletion due to the drain bias is larger than that of the asymmetric TFT. Due to the less carrier concentration in the channel, the asymmetric a-Si:H TFT shows the less VT degradation compared with the symmetric TFT.

EFFECT OF GATE OXIDE PROCESSES ON 4H-SiC MOSFETs ON (000-1) ORIENTED SUBSTRATE

2009 ◽  
Vol 19 (01) ◽  
pp. 161-166
Author(s):  
HARSH NAIK ◽  
KE TANG ◽  
T. PAUL CHOW
Keyword(s):  
Low Temperature ◽  
Carrier Concentration ◽  
Threshold Voltage ◽  
Hall Mobility ◽  
Field Effect ◽  
Gate Oxide ◽  
Field Effect Mobility ◽  
Plasma Enhanced Cvd ◽  
And Inversion

We have fabricated, characterized and compared the performance of lateral n -channel 4 H - SiC MOSFETs on (000-1) oriented substrates, using two different gate oxide processes. These processes include low-temperature deposited oxide and plasma-enhanced CVD oxide. Different MOSFET parameters, such as field-effect mobility, threshold voltage, Hall mobility and inversion sheet carrier concentration has been compared for the two processes.

Sign in / Sign up

Export Citation Format

Share Document