A Low-Cost Soft Error Tolerant Read Circuit for Single/Multi-Level Cross-Point RRAM Arrays

Author(s):  
Hossein Bardareh ◽  
Amir M. Hajisadeghi ◽  
Hamid R. Zarandi
Keyword(s):  
Low Cost ◽  
2013 ◽  
Vol 534 ◽  
pp. 131-135
Author(s):  
You Yin ◽  
Rosalena Irma Alip ◽  
Yu Long Zhang ◽  
Ryota Kobayashi ◽  
Sumio Hosaka

Here, we report multi-level storage (MLS) in multi-layer (ML) and single-layer (SL) phase change memories (PCM). For the former ML-PCM device, the active medium with two layers of chalcogenide consists of a top 30 nm TiN/180 nm SbTeN/20 nm TiN/bottom 120 nm SbTeN stacked multi-layer. Three stable and distinct resistance states are demonstrated in both static and dynamic switching characteristics of the multi-layer devices. For the latter SL-PCM device, the active medium with only one layer of chalcogenide consists of a top 50 nm TiN/150 nm SbTeN. We demonstrate that the number of distinguishable resistance levels can readily reach 16 and even higher. These levels in this study result from the initial threshold switching and the subsequent current-controlled crystallization induced by Joule heating. Therefore, the latter memory allows the creation of many distinct levels, thus enabling the low-cost ultra-high-density non-volatile memory.


Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2101
Author(s):  
Yohan Ko

The exponentially increasing occurrence of soft errors makes the optimization of reliability, performance, hardware area, and power consumption one of the main concerns in modern embedded processors. Since the design cost of hardware techniques aimed at improving the reliability of microprocessors is quite expensive for resource-constrained embedded systems, software-level fault tolerance mechanisms have been proposed as an attractive solution for soft error threats. However, many software-level redundancy-based schemes are accompanied by considerable performance overhead, which is not acceptable for many embedded applications. In this work, we have introduced an ultra-low-cost soft error protection scheme for embedded applications, which works based on source-code analysis and identifying critical variables. After identification, these vital variables are adequately protected by placing runtime checks at critical points of execution. Our experimental results based on several applications demonstrate that the proposed scheme can mitigate the failure rate by 47% with negligible performance degradation.


2011 ◽  
Vol 42 (12) ◽  
pp. 2082-2092 ◽  
Author(s):  
Javier Toral Vazquez ◽  
Bruno Castanié ◽  
Jean-Jacques Barrau ◽  
Nicolas Swiergiel

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