A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme

2002 ◽  
Author(s):  
H. Yamauchi ◽  
T. Iwata ◽  
H. Akamatsu ◽  
A. Matsuzawa
Keyword(s):  
Cell Architecture ◽  
Sram Cell

A New Approach for SRAM Soft Defect Root Cause Identification

2007 ◽  
Author(s):  
Peter Egger ◽  
Stefan Müller ◽  
Martin Stiftinger
Keyword(s):  
Integrated Circuits ◽  
Top Down ◽  
Feature Size ◽  
Design Rules ◽  
New Approach ◽  
Root Cause ◽  
Wafer Fab ◽  
Sram Cell ◽  
Tcad Simulation ◽  
Root Cause Identification

Abstract With shrinking feature size of integrated circuits traditional FA techniques like SEM inspection of top down delayered devices or cross sectioning often cannot determine the physical root cause. Inside SRAM blocks the aggressive design rules of transistor parameters can cause a local mismatch and therefore a soft fail of a single SRAM cell. This paper will present a new approach to identify a physical root cause with the help of nano probing and TCAD simulation to allow the wafer fab to implement countermeasures.

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