A 0.5 V/100 MHz over-V/sub CC/ grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes

2002 ◽  
Author(s):  
H. Yamauchi ◽  
T. Iwata ◽  
H. Akamatsu ◽  
A. Matsuzawa
Keyword(s):  
Data Storage ◽  
Cell Architecture ◽  
Sram Cell

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

Non Volatile Memory Technologies: Floating Gate Concept Evolution

2004 ◽  
Vol 830 ◽  
Author(s):  
Cesare Clementi ◽  
Roberto Bez
Keyword(s):  
Data Storage ◽  
Flash Memory ◽  
Floating Gate ◽  
Nand Flash ◽  
Know How ◽  
Technology Node ◽  
Cell Architecture ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
The Cost

ABSTRACTThe most relevant phenomenon of this last decade in the field of semiconductor memories has been the explosive growth of the Flash memory market, driven by cellular phones and other types of electronic portable equipments (palm top, mobile PC, mp3 audio player, digital camera and so on). Moreover, in the coming years portable systems will ask even more non volatile memories either with high density and very high writing throughput for data storage application, or with fast random access for code execution in place. The strong consolidated know-how (more than ten years of experience), the flexibility and the cost make the floating gate Flash Memory a largely utilized, well-consolidated and mature technology for most of the non-volatile memory application. Today Flash sales represent a considerable amount of the overall semiconductor market.Nowadays two of the several cell architecture proposed up to now can be considered as industry standard: the common ground NOR Flash that due to its versatility is addressing both the code and data storage segments and the NAND Flash, optimized for the data storage market.The exploitation of the multilevel approach at each technology node allows the increase of the memory efficiency, about doubling the density at the same chip size, widening the application range and reducing the cost per bit.In this paper the main issues related to both NOR and NAND Flash memory technology will be summarized, with the aim of describing both the basic functionality of the memory cell and the main cell architecture today consolidated. Both cells are basically a floating-gate MOS transistor, programmed by channel hot electron (NOR) or by Fowler-Nordheim tunneling (NAND) and erased by Fowler-Nordheim tunnel. The main reliability properties, charge retention and endurance, are presented, together with some comments on the basic physical mechanisms responsible for.A couple of innovative approaches to floating gate cell evolution, namely nanocrystal memory and 3-D cell will be described.Finally the Flash cell scaling issues will be covered, pointing out the main challenges. The Flash cell scaling has been demonstrated to be really possible and to be able to follow the Moore's law down to the 90 nm technology generations. The technology development and the consolidated know-how are expected to sustain the scaling trend down to the 50 nm technology node and below as forecasted by the ITRS roadmap.

A read-disturb-free stable low power and high-density GNRFET 6T SRAM with multi-VT technology

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 203-214
Author(s):  
Pramod Kumar Patel ◽  
M.M. Malik ◽  
Tarun Kumar Gutpa
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Supply Voltage ◽  
Early Stage ◽  
Process Variation ◽  
High Density ◽  
Oxide Semiconductor ◽  
Mass Storage ◽  
Content Type ◽  
Sram Cell

Purpose The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate at the minimum supply voltage of 325 mV, whereas the conventional Si-CMOS 6 T SRAM unable to operate below 725 mV, which result in an acceptable failure rate.The advance of Si-CMOS (complementary metal-oxide-semiconductor) based 6 T SRAM cell faces inherent limitation with aggressive downscaling. Hence, there is a need to propose alternatives for the conventional cells. Design/methodology/approach This study aims to improve the performance of the conventional 6T SRAM cell using dual threshold technology, device sizing, optimization of supply voltage under process variation with GNRFET technology. Further performance can be enhanced by resolving half-select issue. Findings The GNRFET-based 6T SRAM cell demonstrates that it is capable of continued improve the performance under the process, voltage, and temperature (PVT) variations significantly better than its CMOS counterpart. Research limitations/implications Nano-material fabrication technology of GNRFETs is in the early stage; hence, the different transistor models can be used to evaluate the parameters of future GNRFETs circuit. Practical implications GNRFET devices are suitable for implementing low power and high density SRAM cell. Social implications The conventional Si-CMOS 6 T SRAM cell is a core component and used as the mass storage element in cache memory in computer system organization, mobile phone and other data storage devices. Originality/value This paper presents a new approach to implement an alternative design of GNRFET -based 6T SRAM cell with doped reservoirs that also supports process variation. In addition, multi-threshold technology optimizes the performance of the proposed cell. The proposed design provides a means to analyze delay and power of GNRFET-based SRAM under process variation with considering edge roughness, and offers design and fabrication insights for cell in the future.

scholarly journals Design of Low Power 4bit 6T-Sram Cell for Data Storage using Finfet 32NM Technology

2019 ◽  
Vol 9 (2) ◽  
pp. 1070-1077
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Cell Structure ◽  
Current Control ◽  
Access Time ◽  
Noise Margin ◽  
Nanoscale System ◽  
Sram Cell ◽  
Static Power ◽  
Temperature Impact

The presentation of the proposed FinFET based 6T SRAM cell has been assessed for its activity in low control space, indicating less SCEs, ultra little access time and high steadiness. The static clamor edge, spillage current, control dissemination and sub-limit current of FinFET based 6T SRAM cell at 32nm has been contrasted and MOSFET based 6T SRAM cell at 32nm innovation hub. It has been seen during the reproduction that the deferral among compose and read and power dissipation of FinFET based 6T SRAM cell is radically decreased when contrasted and regular MOSFET based 6T SRAM cell. The static power dissemination with differing width of Load, Driver and Access transistor of FinFET based model has additionally been weighed against MOSFET based model. At last, control dissemination and static clamor edge at 32nm for both MOSFET and FinFET based 6T SRAM cell have been contrasted all together with comprehend the subjectively conduct of the cell at various innovation hubs of the proposed FinFET model. It tends to be valued that the gadgets without anyone else's input don't add to the current joining period. Yet, until, a circuit investigation utilizing the proposed gadgets is attempted, the full advantages of joining can't be caught. Rationale and memory circuit plan in Nano scale system requires power over spillage flows with gadget level parameter varieties. After the wonderful decrease in Leakage current and power dissemination, a similar methodology is then executed to cutting edge SRAM cells. We have thought about different progressed proposed FinFET based SRAM cells with the customary progressed MOSFET based SRAM cells. The huge spillage decrease has been seen when we have changed from traditional MOSFET models to FinFET models. Finally, process parametric varieties at circuit level, gadget level and material level on FinFET based 6T SRAM cell is talked about and the instrument to control these varieties is introduced in the proposal. Procedure parametric varieties like word line, bit line, control supply tweaks is appeared and examined. Temperature impact is likewise appeared and talked about in the postulation. Every one of the recreations have been performed on Cadence Virtuoso at 45 nm innovation. Our investigation demonstrates that, utilization of FinFET gadget with characteristic body decreases spillage current and improves the driving capacity. Consequently, we presume that FinFET can develop as one of the promising possibility for decreasing spillage segments making it effective for low power and superior SRAM cell structure in nanoscale system. In this paper SRAM investigation as far as Static Noise Margin, Data Retention Voltage,

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