A high performance 2.4 Mb L1 and L2 cache compatible 45nm SRAM with yield improvement capabilities

2008 ◽  
Author(s):  
R. Joshi ◽  
R. Houle ◽  
D. Rodko ◽  
P. Patel ◽  
W. Huott ◽  
...  
Keyword(s):  
High Performance ◽  
Yield Improvement ◽  
L2 Cache ◽  
L1 And L2

Designing of High Performance Multicore Processor with Improved Cache Configuration and Interconnect

2016 ◽  
pp. 204-219
Author(s):  
Ram Prasad Mohanty ◽  
Ashok Kumar Turuk ◽  
Bibhudatta Sahoo
Keyword(s):  
High Performance ◽  
Multicore Processors ◽  
Multicore Processor ◽  
Cache Size ◽  
L2 Cache ◽  
Internal Network ◽  
On Chip ◽  
L1 And L2 ◽  
The Impact ◽  
Cache Configuration

The growing number of cores increases the demand for a powerful memory subsystem which leads to enhancement in the size of caches in multicore processors. Caches are responsible for giving processing elements a faster, higher bandwidth local memory to work with. In this chapter, an attempt has been made to analyze the impact of cache size on performance of Multi-core processors by varying L1 and L2 cache size on the multicore processor with internal network (MPIN) referenced from NIAGRA architecture. As the number of core's increases, traditional on-chip interconnects like bus and crossbar proves to be low in efficiency as well as suffer from poor scalability. In order to overcome the scalability and efficiency issues in these conventional interconnect, ring based design has been proposed. The effect of interconnect on the performance of multicore processors has been analyzed and a novel scalable on-chip interconnection mechanism (INOC) for multicore processors has been proposed. The benchmark results are presented by using a full system simulator. Results show that, using the proposed INoC, compared with the MPIN; the execution time are significantly reduced.

Fuzzy Logic-Based DSE Engine: Reconfiguration for Optimization of Multicore Architectures

2016 ◽  
Vol 25 (12) ◽  
pp. 1650160
Author(s):  
Iqra Farhat ◽  
Muhammad Yasir Qadri ◽  
Nadia N. Qadri ◽  
Jameel Ahmed
Keyword(s):  
Fuzzy Logic ◽  
Energy Consumption ◽  
Design Space Exploration ◽  
Design Space ◽  
Multicore Architectures ◽  
L2 Cache ◽  
On Chip ◽  
L1 And L2 ◽  
The Impact ◽  
Target Design

Moore’s law has been one of the reason behind the evolution of multicore architectures. Modern multicore architectures offer great amount of parallelism and on-chip resources that remain underutilized. This is partly due to inefficient resource allocation by operating system or application being executed. Consequently the poor resource utilization results in greater energy consumption and less throughput. This paper presents a fuzzy logic-based design space exploration (DSE) approach to reconfigure a multicore architecture according to workload requirements. The target design space is explored for L1 and L2 cache size and associativity, operating frequency, and number of cores, while the impact of various configurations of these parameters is analyzed on throughput, miss ratios for L1 and L2 cache and energy consumption. MARSSx86, a cycle accurate simulator, running various SPALSH-2 benchmark applications has been used to evaluate the architecture. The proposed fuzzy logic-based DSE approach resulted in reduction in energy consumption along with an overall improved throughput of the system.

scholarly journals Poluição de Cache e Thrashing em Aplicações Paralelas de Alto Desempenho

2019 ◽  
Author(s):  
Arthur Krause ◽  
Francis Moreira ◽  
Valéria Girelli ◽  
Philippe Olivier Navaux
Keyword(s):  
High Performance ◽  
Computer Systems ◽  
Memory Access ◽  
Replacement Policy ◽  
Parallel Applications ◽  
Access Time ◽  
L2 Cache ◽  
Intelligent Management

Conforme os processadores evoluem, o desempenho dos sistemas computacionais se torna cada vez mais limitado pelo tempo de acesso à memória. Caches são empregadas a fim de contornar este problema, mas é necessária uma gerência inteligente dos dados que são armazenados nelas para impedir que problemas como poluição e thrashing degradem seu desempenho. Neste trabalho é apresentada uma análise da poluição de cache e thrashing em aplicações paralelas de alto desempenho. Os resultados mostram que caches com maior associatividade sofrem mais com estes problemas. Até 28% dos cache misses na L1 poderiam ser evitados com uma política de substituição de cache mais inteligente, chegando a até 62% na cache L2 e 98% na LLC. As processors evolve, the performance of computer systems becomes increasingly limited by the memory access time. Caches are employed in order to get around this problem, but an intelligent management of the data that is stored in them is necessary to prevent problems such as pollution and thrashing from degrading their performance. In this work, an analysis of cache and thrashing pollution in high performance parallel applications is presented. The results show that caches with greater associativity suffer more from these problems. Up to 28% of cache misses in the L1 cache could be avoided with a smarter replacement policy, up to 62% in the L2 cache and 98% in the LLC.

Alkaline phosphatase isoenzymes in serum determined by high-performance anion-exchange liquid chromatography with detection by enzyme reaction.

1988 ◽  
Vol 34 (12) ◽  
pp. 2406-2409 ◽  
Author(s):  
M T Parviainen ◽  
J H Galloway ◽  
J H Towers ◽  
J A Kanis
Keyword(s):  
Alkaline Phosphatase ◽  
Liquid Chromatography ◽  
Anion Exchange ◽  
High Performance ◽  
Enzyme Reaction ◽  
Anion Exchange Column ◽  
Alkaline Phosphatase Isoenzymes ◽  
On Line ◽  
Reproducible Method ◽  
L1 And L2

Abstract This rapid, reproducible method for separating and determining individual alkaline phosphatase (EC 3.1.3.1) isoenzymes in serum is based on high-performance liquid chromatography with a weak anion-exchange column (SynChropak AX 300). The isoenzymes so resolved are detected by using an on-line enzyme reaction followed by spectrophotometric monitoring at 405 nm of the 4-nitrophenol formed. Complete diagnostic profiles of the various isoenzymes present in normal and pathological sera are obtained within 20 min. The mean (and SD) normal concentrations of the bone B1 and intestinal isoenzymes in serum of adults were 3.7 (4.3) and 4.5 (3.9) U/L, respectively (n = 14), and of the bone isoenzyme B2 and liver isoenzymes L1 and L2, 5.8 (8.6), 33.0 (10.6), and 12.0 (4.8) U/L, respectively (n = 17). Concentrations of the B2 and L1 isoenzymes in adults over age 40 years differed significantly from those in adults younger than 40 years, that of bone isoenzyme being lower (P less than 0.05) and that of the liver isoenzyme being higher (P less than 0.001) in the younger adults.

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