Designing of High Performance Multicore Processor with Improved Cache Configuration and Interconnect

2016 ◽  
pp. 204-219
Author(s):  
Ram Prasad Mohanty ◽  
Ashok Kumar Turuk ◽  
Bibhudatta Sahoo
Keyword(s):  
High Performance ◽  
Multicore Processors ◽  
Multicore Processor ◽  
Cache Size ◽  
L2 Cache ◽  
Internal Network ◽  
On Chip ◽  
L1 And L2 ◽  
The Impact ◽  
Cache Configuration

The growing number of cores increases the demand for a powerful memory subsystem which leads to enhancement in the size of caches in multicore processors. Caches are responsible for giving processing elements a faster, higher bandwidth local memory to work with. In this chapter, an attempt has been made to analyze the impact of cache size on performance of Multi-core processors by varying L1 and L2 cache size on the multicore processor with internal network (MPIN) referenced from NIAGRA architecture. As the number of core's increases, traditional on-chip interconnects like bus and crossbar proves to be low in efficiency as well as suffer from poor scalability. In order to overcome the scalability and efficiency issues in these conventional interconnect, ring based design has been proposed. The effect of interconnect on the performance of multicore processors has been analyzed and a novel scalable on-chip interconnection mechanism (INOC) for multicore processors has been proposed. The benchmark results are presented by using a full system simulator. Results show that, using the proposed INoC, compared with the MPIN; the execution time are significantly reduced.

Fuzzy Logic-Based DSE Engine: Reconfiguration for Optimization of Multicore Architectures

2016 ◽  
Vol 25 (12) ◽  
pp. 1650160
Author(s):  
Iqra Farhat ◽  
Muhammad Yasir Qadri ◽  
Nadia N. Qadri ◽  
Jameel Ahmed
Keyword(s):  
Fuzzy Logic ◽  
Energy Consumption ◽  
Design Space Exploration ◽  
Design Space ◽  
Multicore Architectures ◽  
L2 Cache ◽  
On Chip ◽  
L1 And L2 ◽  
The Impact ◽  
Target Design

Moore’s law has been one of the reason behind the evolution of multicore architectures. Modern multicore architectures offer great amount of parallelism and on-chip resources that remain underutilized. This is partly due to inefficient resource allocation by operating system or application being executed. Consequently the poor resource utilization results in greater energy consumption and less throughput. This paper presents a fuzzy logic-based design space exploration (DSE) approach to reconfigure a multicore architecture according to workload requirements. The target design space is explored for L1 and L2 cache size and associativity, operating frequency, and number of cores, while the impact of various configurations of these parameters is analyzed on throughput, miss ratios for L1 and L2 cache and energy consumption. MARSSx86, a cycle accurate simulator, running various SPALSH-2 benchmark applications has been used to evaluate the architecture. The proposed fuzzy logic-based DSE approach resulted in reduction in energy consumption along with an overall improved throughput of the system.

Study on Heat Conduction in a Simulated Multicore Processor Chip—Part II: Case Studies

2013 ◽  
Vol 135 (2) ◽  
Author(s):  
Wataru Nakayama
Keyword(s):  
Hot Spots ◽  
High Performance ◽  
Thermal Environment ◽  
Hot Spot ◽  
Air Cooling ◽  
Multicore Processor ◽  
Temperature Contrast ◽  
On Chip ◽  
Heat Spreading ◽  
Level Analysis

The objective of this study is to understand the effects of various parameters involved in the chip design and cooling on the occurrence of hot spots on a multicore processor chip. The thermal environment for the die is determined by the cooling design which differs distinctly between different classes of electronic equipment. In the present study, like many other hot spot studies, the effective heat transfer coefficient represents the thermal environment for the die, but, its representative values are derived for different cooling schemes in order to examine in what classes of electronic equipment the hot spot concern grows. The cooling modes under study are high-performance air-cooling, high-performance liquid-cooling, conventional air-cooling, and oil-cooling in infrared radiation (IR) thermography setup. Temperature calculations were performed on a model which is designed to facilitate the study of several questions that have not been fully addressed in the existing literature. These questions are concerned with the granularity of power and temperature distributions, thermal interactions between circuits on the die, the roles of on-chip wiring layer and the buried dioxide in heat spreading, and the mechanism of producing temperature contrast across the die. The main results of calculations are the temperature of the target spot and the temperature contrast across the die. Temperature contrasts are predicted in a range 10–25 K, and the results indicate that a major part of the temperature contrast is formed at a granularity corresponding to the size of functional units on actual microprocessor chips. At a fine granularity level and under a scenario of high power concentration, the on-chip wiring layer and the buried oxide play some roles in heat spreading, but their impact on the temperature is generally small. However, the details of circuits need to be taken into account in future studies in order to investigate the possibility of nanometer-scale hot spots. Attention is also called to the need to understand the effect of temperature nonuniformity on the processor performance for which low temperature at inactive cells makes a major contribution. In contrast to the situation for the die under forced convection cooling, the die in passively cooled compact equipment is in distinctly different thermal environment. Strong thermal coupling between the die and the system structure necessitates the integration of package and system level analysis with the die-level analysis.

scholarly journals EFFECTS OF A BARRIER LAYER IN INGAAS CHANNEL MOSFETS FOR ANALOG/ MIXED SIGNAL SYSTEM-ON-CHIP APPLICATIONS

2014 ◽  
pp. 281-284
Author(s):  
SUCHISMITA TEWARI ◽  
ABHIJIT BISWAS ◽  
ABHIJIT MALLIK
Keyword(s):  
Barrier Layer ◽  
Electron Mobility ◽  
High Performance ◽  
Cutoff Frequency ◽  
Analog Performance ◽  
Unity Gain ◽  
On Chip ◽  
The Impact ◽  
First Time ◽  
Ingaas Mosfet

Addition of a barrier layer in an InGaAs MOSFET, which shows promise for high performance logic applications due to enhanced electron mobility, further improves the electron mobility. We report, for the first time, a detailed investigation of the impact of different barrier layers on the analog performance of an InGaAs MOSFET. The device parameters for analog applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/IDS), drain conductance (gd), intrinsic gain, and unity-gain cutoff frequency (fT) are studied with the help of a device simulator. A barrier layer is found to improve the analog performance of such a device in general; with a double-barrier layer showing the best performance.

Wireless CNC Motion Controller Designed with PSoC

2014 ◽  
Vol 898 ◽  
pp. 944-951 ◽  
Author(s):  
Chi Zhang ◽  
Zhao Hui Ye ◽  
Yong Ming Zhou
Keyword(s):  
High Performance ◽  
System On Chip ◽  
Numerical Control ◽  
Motion Controller ◽  
Joint Axis ◽  
Chip Technology ◽  
On Chip ◽  
Cnc Controller ◽  
The Impact ◽  
Circular Interpolation

Numerical control (NC) technology is a kind of technology combined with electronics, machinery manufacturing, and other interdisciplinary combination of technologies. It is an important part of modern manufacturing. Currently, NC technology is developing towards the open CNC system with extensibility and interchangeability, while the modern electronic technology is developing towards the programmable technology and SoC (System-on-Chip) technology. However, current CNC controller designed with SoC is still in the research stage and not practical yet. In this paper, a practical CNC motion controller is built with modern PSoC (Programmable System-on-Chip) with wireless Ethernet interface. This controller has a high-performance microprocessor, numbers of free configurable analog and digital devices and IO (input/output) interfaces, and many kinds of communication interfaces. Therefore, it has good real-time control functions and communication functions. Experiments for controlling a three joint-axis engraving machine show that the controller can achieve high performance of parallel control of the three joint-axis linear interpolation and two joint-axis circular interpolation, and high performance of the trapezoidal and S-shape speed control. In addition, in order to reduce the impact to the motor and increase the system efficiency, a kind of look-ahead algorithm for velocity control with low time cost is used.

An Embedded Multicore Platform Exploration in Video Application Utilizing FPGA

2012 ◽  
Vol 505 ◽  
pp. 329-337
Author(s):  
Chun Hua Xiao ◽  
Zhang Qin Huang ◽  
Da Li
Keyword(s):  
High Performance ◽  
New Technology ◽  
Practical Significance ◽  
Single Chip ◽  
Multicore Processor ◽  
Design Problems ◽  
Video Application ◽  
Multiple Cores ◽  
Field Programmable ◽  
On Chip

Multi-processor is not a new technology, but with the development of modern silicon technology, it is possible to integrate multiple cores in a single chip package, which is called multicore processor. Whether in the desktop personal machine, or embedded applications, multicore processor has been a general trend, due to the requirement of high performance and design problems in single-core processor. Surrounded multi-screen provides a better sense of reality, which is widely used in the surveillance, military, exhibitions, and so on. With the advantages in parallel processing, multicore technology has an important practical significance and a broad prospect in these applications. In this paper, an exploration on multicore architecture is mainly focused on, from the perspectives of processing elements, memory hierarchy, and on-chip interconnection. A basic platform for multi-screen display is implemented on the Xilinx field programmable gate array (FPGA), and it illustrates that there is a 3.6 times higher performance than the corresponding single-core design, which provides a helpful guidance and revelation to further researches.

scholarly journals Multiprotocol Authentication Device for HPC and Cloud Environments Based on Elliptic Curve Cryptography

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1148
Author(s):  
Antonio F. Díaz ◽  
Ilia Blokhin ◽  
Mancia Anguita ◽  
Julio Ortega ◽  
Juan J. Escobar
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
High Performance ◽  
Low Cost ◽  
System On Chip ◽  
Access To Services ◽  
Multifactor Authentication ◽  
Server Systems ◽  
On Chip ◽  
The Impact

Multifactor authentication is a relevant tool in securing IT infrastructures combining two or more credentials. We can find smartcards and hardware tokens to leverage the authentication process, but they have some limitations. Users connect these devices in the client node to log in or request access to services. Alternatively, if an application wants to use these resources, the code has to be amended with bespoke solutions to provide access. Thanks to advances in system-on-chip devices, we can integrate cryptographically robust, low-cost solutions. In this work, we present an autonomous device that allows multifactor authentication in client–server systems in a transparent way, which facilitates its integration in High-Performance Computing (HPC) and cloud systems, through a generic gateway. The proposed electronic token (eToken), based on the system-on-chip ESP32, provides an extra layer of security based on elliptic curve cryptography. Secure communications between elements use Message Queuing Telemetry Transport (MQTT) to facilitate their interconnection. We have evaluated different types of possible attacks and the impact on communications. The proposed system offers an efficient solution to increase security in access to services and systems.

scholarly journals On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-14 ◽  
Author(s):  
Khader Mohammad ◽  
Ahsan Kabeer ◽  
Tarek Taha
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Chip Multiprocessors ◽  
Data Transfer ◽  
High Volume ◽  
Power Minimization ◽  
Processor Core ◽  
L2 Cache ◽  
Data Bus ◽  
On Chip

In chip-multiprocessors (CMP) architecture, the L2 cache is shared by the L1 cache of each processor core, resulting in a high volume of diverse data transfer through the L1-L2 cache bus. High-performance CMP and SoC systems have a significant amount of data transfer between the on-chip L2 cache and the L3 cache of off-chip memory through the power expensive off-chip memory bus. This paper addresses the problem of the high-power consumption of the on-chip data buses, exploring a framework for memory data bus power consumption minimization approach. A comprehensive analysis of the existing bus power minimization approaches is provided based on the performance, power, and area overhead consideration. A novel approaches for reducing the power consumption for the on-chip bus is introduced. In particular, a serialization-widening (SW) of data bus with frequent value encoding (FVE), called the SWE approach, is proposed as the best power savings approach for the on-chip cache data bus. The experimental results show that the SWE approach with FVE can achieve approximately 54% power savings over the conventional bus for multicore applications using a 64-bit wide data bus in 45 nm technology.

Dietary Vitamin and Stability of Oral Anticoagulation: Proposal of a Diet with Constant Vitamin K1 Content

1997 ◽  
Vol 77 (03) ◽  
pp. 504-509 ◽  
Author(s):  
Sarah L Booth ◽  
Jacqueline M Charnley ◽  
James A Sadowski ◽  
Edward Saltzman ◽  
Edwin G Bovill ◽  
...  
Keyword(s):  
Dietary Intake ◽  
Vitamin K ◽  
High Performance ◽  
Case Reports ◽  
Food Composition ◽  
Dietary Guidelines ◽  
Dietary Vitamin ◽  
Vitamin K1 ◽  
The Stability ◽  
The Impact

SummaryCase reports cited in Medline or Biological Abstracts (1966-1996) were reviewed to evaluate the impact of vitamin K1 dietary intake on the stability of anticoagulant control in patients using coumarin derivatives. Reported nutrient-drug interactions cannot always be explained by the vitamin K1 content of the food items. However, metabolic data indicate that a consistent dietary intake of vitamin K is important to attain a daily equilibrium in vitamin K status. We report a diet that provides a stable intake of vitamin K1, equivalent to the current U.S. Recommended Dietary Allowance, using food composition data derived from high-performance liquid chromatography. Inconsistencies in the published literature indicate that prospective clinical studies should be undertaken to clarify the putative dietary vitamin K1-coumarin interaction. The dietary guidelines reported here may be used in such studies.

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