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High performance 60 nm CMOS technology enhanced with BST (body-slightly-tied) structure SOI and Cu/low-k (k=2.9) interconnect for microprocessors
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)
◽
10.1109/vlsit.2002.1015436
◽
2003
◽
Author(s):
I. Kudo
◽
S. Miyake
◽
T. Syo
◽
S. Maruyama
◽
Y. Yama
◽
...
Keyword(s):
High Performance
◽
Cmos Technology
◽
Low K
Download Full-text
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A high performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)
◽
10.1109/vlsit.2000.852818
◽
2002
◽
Cited By ~ 7
Author(s):
P. Smeys
◽
V. McGahay
◽
I. Yang
◽
J. Adkisson
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K. Beyer
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...
Keyword(s):
High Performance
◽
Cmos Technology
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Cu Interconnects
◽
Low K
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Soi Cmos
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Highly stable partial body tied SOI CMOS technology with Cu interconnect and low-k dielectric for high performance microprocessor
IEEE International SOI Conference SOI-02
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10.1109/soi.2002.1044443
◽
2002
◽
Cited By ~ 1
Author(s):
Kim
◽
Oh
◽
Kang
◽
Oh
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Yoo
◽
...
Keyword(s):
High Performance
◽
Cmos Technology
◽
Partial Body
◽
Cu Interconnect
◽
Low K
◽
Soi Cmos
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An enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications
2014 IEEE International Electron Devices Meeting
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10.1109/iedm.2014.7046970
◽
2014
◽
Cited By ~ 9
Author(s):
Shien-Yang Wu
◽
C.Y. Lin
◽
M.C. Chiang
◽
J.J. Liaw
◽
J.Y. Cheng
◽
...
Keyword(s):
Low Power
◽
High Performance
◽
Cmos Technology
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Low K
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A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications
International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)
◽
10.1109/iedm.2000.904382
◽
2002
◽
Cited By ~ 16
Author(s):
K.K. Young
◽
S.Y. Wu
◽
C.C. Wu
◽
C.H. Wang
◽
C.T. Lin
◽
...
Keyword(s):
High Performance
◽
Cmos Technology
◽
193 Nm
◽
Low K
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A 0.11 μm CMOS technology with copper and very-low-k interconnects for high-performance system-on-a-chip cores
International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)
◽
10.1109/iedm.2000.904381
◽
2002
◽
Cited By ~ 5
Author(s):
Y. Takao
◽
H. Kudo
◽
J. Mitani
◽
Y. Kotani
◽
S. Yamaguchi
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Keyword(s):
High Performance
◽
Cmos Technology
◽
Performance System
◽
System On A Chip
◽
Low K
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A 100 nm copper/low-k bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)
◽
10.1109/vlsit.2002.1015370
◽
2003
◽
Cited By ~ 4
Author(s):
G.C.-F. Yeap
◽
J. Chen
◽
P. Grudowski
◽
Y. Jeon
◽
Y. Shiho
◽
...
Keyword(s):
High Performance
◽
Gate Oxide
◽
Cmos Technology
◽
System On Chip
◽
Analog System
◽
Standby Power
◽
On Chip
◽
Low K
Download Full-text
High-performance 80-nm gate length SOI-CMOS technology with copper and very-low-k interconnects
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)
◽
10.1109/vlsit.2000.852819
◽
2002
◽
Cited By ~ 4
Author(s):
K. Sukegawa
◽
M. Yamaji
◽
K. Yoshie
◽
K. Furumochi
◽
T. Maruyama
◽
...
Keyword(s):
High Performance
◽
Cmos Technology
◽
Gate Length
◽
Low K
◽
Soi Cmos
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High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology
2007 IEEE International Electron Devices Meeting
◽
10.1109/iedm.2007.4418915
◽
2007
◽
Cited By ~ 14
Author(s):
T. Miyashita
◽
K. Ikeda
◽
Y. S. Kim
◽
T. Yamamoto
◽
Y. Sambonsugi
◽
...
Keyword(s):
Low Power
◽
High Performance
◽
Multiple Stressors
◽
Cmos Technology
◽
Enhanced Strain
◽
Low K
Download Full-text
A Simple Sub-0.3/spl mu/m CMOS Technology With Five-level Interconnect Using Al-plug And HSQ Of Low-k For High Performance Processor
Symposium on VLSI Technology
◽
10.1109/vlsit.1997.623692
◽
1997
◽
Cited By ~ 1
Author(s):
Yoshiyama
◽
Okada
◽
Igarashi
◽
Yamada
◽
Shimizu
◽
...
Keyword(s):
High Performance
◽
Cmos Technology
◽
Low K
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A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability
Microelectronics Reliability
◽
10.1016/s0026-2714(01)00233-5
◽
2002
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Vol 42
(1)
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pp. 15-25
◽
Cited By ~ 4
Author(s):
Yoshihiro Takao
◽
Hiroshi Kudo
◽
Junichi Mitani
◽
Yoshiyuki Kotani
◽
Satoshi Yamaguchi
◽
...
Keyword(s):
High Performance
◽
Cmos Technology
◽
Low K
Download Full-text
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