scholarly journals Sensitivity of Solder Joint Fatigue to Sources of Variation in Advanced Vehicular Power Electronics Cooling

Author(s):  
Andreas Vlahinos ◽  
Michael O’Keefe

This paper demonstrates a methodology for taking variation into account in the thermal and fatigue analyses of the die attach for an inverter of an electric traction drive vehicle. This method can be used to understand how variation and mission profile affect parameters of interest in a design. Three parameters are varied to represent manufacturing, material, and loading variation: solder joint voiding, aluminum nitride substrate thermal conductivity, and heat generation at the integrated gate bipolar transistor, or IGBT. The influence of these parameters on temperature and solder fatigue life is presented. The heat generation loading variation shows the largest influence on the results for the assumptions used in this problem setup.

1991 ◽  
Vol 113 (2) ◽  
pp. 121-128 ◽  
Author(s):  
R. G. Ross

Differential expansion induced fatigue resulting from temperature cycling is a leading cause of solder joint failures in spacecraft. Achieving high reliability flight hardware requires that each element of the fatigue issue be addressed carefully. This includes defining the complete thermal-cycle environment to be experienced by the hardware, developing electronic packaging concepts that are consistent with the defined environments, and validating the completed designs with a thorough qualification and acceptance test program. This paper describes a useful systems approach to solder fatigue based principally on the fundamental log-strain versus log-cycles-to-failure behavior of fatigue. This fundamental behavior has been useful to integrate diverse ground test and flight operational thermal-cycle environments into a unified electronics design approach. Each element of the approach reflects both the mechanism physics that control solder fatigue, as well as the practical realities of the hardware build, test, delivery, and application cycle.


2003 ◽  
Vol 125 (4) ◽  
pp. 582-588 ◽  
Author(s):  
X. J. Zhao ◽  
G. Q. Zhang ◽  
J. F. J. M. Caers ◽  
L. J. Ernst

In this paper, an “interfacial boundary volume” based damage criterion was proposed in combination with the modified Coffin-Manson model to predict solder fatigue. This criterion assumes that mainly, the behavior of the thin solder layer at chip pad interface contributes to the solder fatigue, not the whole solder joint or the averaged strains from randomly selected elements. The damage parameter was thus calculated by averaging the visco-plastic strain range over the interfacial boundary layer volume in the solder and later related to the corresponding fatigue life of experimental test through least-squares curves fitting to determine the empirical coefficients in the Coffin-Manson equation. As a demonstrator, the solder joint fatigue in wafer level chip scale packaging under thermal shock loading was analyzed. An appropriate constitutive relation from Darveaux was used to model the inelastic deformation of the solder alloy, and the different stress-strain responses resulting from different designs were calculated. The analysis results were used to develop the empirical fatigue model based on the interfacial boundary volume damage criterion and then this fatigue model was used for prediction. The fatigue lives of chip scale packaging with variable solder land size and component size were analyzed using this model. The prediction results match well with those from experimental tests. For this demonstrator, it was also shown that the empirical model based on the interfacial boundary volume criterion was more accurate than the models obtained from other strain averaging methods.


2016 ◽  
Vol 2016 (1) ◽  
pp. 000106-000110
Author(s):  
Jia-Shen Lan ◽  
Stuwart Fan ◽  
Louie Huang ◽  
Mei-Ling Wu

Abstract In this paper, the solder joint failure and the solder joint fatigue life in the Thin-profile Fine-pitch Ball Grid Array (TFBGA) Package was investigated by performing the drop test, and implementing a simulation model. Owing to the need to meet the increasing demands for functionality, microelectronic package reliability can be compromised and has become the key issue when executing drop tests. During impact in drop test, the deformation of PCB due to bending and mechanical shocks can cause solder joint crack. While this is a well-known issue, observing the solder joint responses during the test execution can be a challenge. Therefore, in this work, a simulation model approach has been developed to investigate the stress and strain of the solder joint during the drop test. In this research, the JEDEC Condition B drop test was simulated, characterized by 1500G peak acceleration and 0.5 ms duration. The drop test simulation model was successful in predicting the solder joint fatigue life with different solder joint materials, such as SAC105 and SAC1205N, while also facilitating result comparison to identify the most optimal structure.


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