A Micromachined Manifold Microchannel Cooler

An improved MEMS fabricated, manifold microchannel cooler has been developed for single phase liquid, forced convection. The manifold design uses multiple channel sizes to minimize pressure drop, maximize heat transfer, and improve temperature uniformity across the area of the cooled device. A significant reduction is achieved in thermal resistance between the device and the cooling fluid. This is a critical need in modern electronic components because of the increasing demand for higher power levels and packaging densities. This paper discusses improvements in fabrication, alignment procedure, and packaging in comparison to our previously published work. A wide range of microchannel dimensions have been fabricated and tested to show the effect of channel size on performance. Testing results of the thermal transfer rates will be presented using silicon diodes as heat sources. A 25 mm × 8 mm × 3 mm (thick) silicon cooler was fabricated to cool two 6 mm square devices. The cooler was microfabricated with a silicon three wafer stack and the channels were etched using standard MEMS processing techniques including DRIE. This new device has modified the authors previously published work in a number of ways. First, fabrication sequence has been modified for better depth uniformity and a new alignment technique has been used that incorporates micro ball bearings as passive alignment pins. Second, triangular shaped inlets have been incorporated to further reduce pressure drop. Third, an aluminum nitride layer was incorporated into the layer stack to achieve electrical isolation between the device and the fluid. Finally, thermal characterization has been improved by using aluminum nitride chip resistors as surrogate heat sources with improved reliability and temperature uniformity over the heated area. Dimensional improvements have also been made to improve fluidic performance and lessen the potential of clogging. The manifold channels are 500 μm wide and 1mm deep with a 50 μm fin width. The microchannels are 150 μm deep with a width of 80 μm and a fin width of 40 μm. The aluminum nitride is bonded onto the top of the silicon channels then the chip resistors are bonded with a silver polyimide paste onto the aluminum nitride. The devices fluidic and thermal performance was measured. We have demonstrated an improvement over the previously published manifold microchannel cooler while also demonstrating the use as a multichip module. The manifold microchannel design minimizes the pressure drop across the channel while maximizing cooling potential and temperature uniformity across the area of the device. The experimental results have shown very promising thermal performance of this multi-chip manifold microchannel cooler. Thermal resistances less than 0.4 C/W were measured at flow rates of 400 ccm with a pressure drop of 5.6 psi. Tests were performed with heat fluxes up to 331 W/cm2 with a measured chip temperature rise of only 53C. The results of the testing show very good thermal performance of this device.

Conducting Properties of a Contact Between Open-End Carbon Nanotube and Various Electrodes

The carbon nanotube (CNT) is becoming a promising candidate as electrical interconnects in nanoscale electronics. This paper reports the electronic structure and the electrical conducting properties at the interface between an open-end single wall CNT (SWCNT) and various metal electrodes, such as Al, Au, Cu, and Pd. A simulation cell consisting of an SWCNT with each end connected to the metal electrode was constructed. A voltage bias is prescribed between the left- and right-electrodes to compute the electronic conductance. Due to the electronic structure, the electron density and local density of states (LDOS) are calculated to reveal the interaction behavior at the interfaces. The first-principle quantum mechanical density functional and non-equilibrium Green’s function (NEGF) approaches are adopted to compute the transport coefficient. After that, the voltage-current relation is calculated using the Landauer-Buttiker formalism. The results show that electrons are conducted through the electrode/CNT/electrode two-probe system. The contact electronic resistance is calculated by averaging the values in the low voltage bias regime (0.0–0.1 V), in which the voltage–current relationship is found to be linear. And the electrical contact conductance of electrode/CNT/electrode system show the electrode-type dependent, however, the amplitude for different electrodes is of the same order.

Observations of Changes in Rate Dependent Flow of SnAgCu Solder Alloys Due to Aging

Aging affects both microstructure and behavior [1, 2]. Microstructural changes are driven by dislocation motion and diffusion processes. Together they affect the flow behavior in solder alloys. We address four aspects of solder microstructure and behavior as affected by aging (a) EDS studies on Ag dispersion in Sn matrix (b) a procedure for modeling intermetallic particle growth (c) a model for estimating effective viscosity of solder alloy (d) both primary and secondary creep models to predict aging effects on behavior. Solder samples were aged for different aging times (15, 30, 60, 90 days aging) and at different aging temperatures (25 C, 75 C, 125 C) prior to running creep tests. Another set of solder samples were similarly aged to characterize the microstructure. The creep data for the experiments are from a series of sixty four experiments performed using a micromechanical tester that is specially fitted with a sensitive capacitance gauge (with a resolution of 0.1 microns) to accurately measure viscoplastic responses of solder to applied loads.

A Model to Predict Pore Shape in Solid During Solidification

The shapes of a growing or decaying bubble entrapped by a solidification front are predicted in this work. The bubble results from supersaturation of a dissolved gas in the liquid ahead of the solidification front. Pore formation is one of the most serious issues affecting properties, microstructure, and strength in materials. In this study, the bubble entrapped as a pore in solid are realistically predicted by utilizing perturbation solutions of Young-Laplace equation governing the tiny bubble shape in the literature. The analytical solutions can account for necking of a bubble beyond the solidification front. Satisfying energy, momentum, mass conservation and physico-chemical equilibria on the bubble surface, the predicted time-dependent pore shapes are found to agree with in-situ measurements.

Effects of Silicon Substrate on the Growth of Carbon Nanotubes

Due to their extraordinary electrical, thermal and mechanical properties, carbon nanotubes (CNTs) have been foreseen as potential materials for electronics devices in the future. To integrate CNTs in electronic applications, CNTs would need to be deposited on different types of Si substrate. In this study, CNTs were grown on Ni catalyst layer with four types of substrates, namely Si, n++ Si, p++ Si and SiO2, using Plasma Enhanced Chemical Vapor Deposition (PECVD). The morphology and microstructure of the CNT films were analyzed by scanning electron microscopy (SEM) and Raman spectroscope. It was found that the type of Si substrate has significant effects on CNT growing characteristics. The possible mechanisms for the observed results are proposed. These findings add significant reference value to select deposition conditions suitable for deposition of CNTs on different types of Si substrate.

Liquid Crystal Polymer (LCP) for Characterization of Millimer-Wave Transmission Lines and Bandpass Filters

In this paper, a multi-layer LCP substrate fabrication process was described and millimeter wave transmission lines and filters were designed and fabricated on the LCP substrate. Various transitions from a CPW to a microstrip line with their characteristic impedance being 50 ohms were investigated. The characteristics of the wirebonding assembly for connecting two transmission lines was also examined. The measurement results show that an insertion loss of 1.3 dB at 60 GHz can be achieved for the two-wire bonding trasmisssion line including two transitions from a CPW to a microstrip line.

Bonding Strength and Microstructure of SnAg-Based Solid Liquid Inter-Diffusion Bonds

Solid Liquid Inter-diffusion (SLID) is a new technology used as interconnects in high density and 3 dimensional packages. This manuscript investigates effect of process parameters, pressure, time and temperature on the strength of bonds and microstructure produced using this technology. A full factorial experiment is designed and implemented on the process with these 3 variables at 3 levels using Sn3.5Ag. Bonds’ strength were then measured using a micro-tester and load displacements were monitored. This analysis shows that SLID bonds form at temperatures much higher than melting temperature of the low melting material. It also shows that time is a significant factor. Bonds that are formed under 10 minutes of time do not show a significant amount of intermetallics. Although the elemental percentage of copper is high in the middle of the bond, it does not reach enough to form any of intermetallic compounds of this ternary system. The specimens fabricated under longer time around 1 hour showed a more brittle, intermetallic like behavior.

Leading Indicators of Damage for Prognostication of Leadfree Electronics Subjected to Multiple Thermo-Mechanical Environments

Electronic assemblies deployed in harsh environments may be subjected to multiple thermal environments during the use-life of the equipment. Often the equipment may not have any macro-indicators of damage such as cracks or delamination. Quantification of thermal environments during use-life is often not feasible because of the data-capture and storage requirements, and the overhead on core-system functionality. There is need for tools and techniques to quantify damage in deployed systems in absence of macro-indicators of damage without knowledge of prior stress history. The presented PHM framework is targeted towards high reliability applications such as avionic and space systems. In this paper, Sn3.0Ag0.5Cu alloy packages have been subjected to multiple thermal cycling environments including −55 to 125C and 0 to 100C. Assemblies investigated include area-array packages soldered on FR4 printed circuit cards. The methodology involves the use of condition monitoring devices, for gathering data on damage pre-cursors at periodic intervals. Damage-state interrogation technique has been developed based on the Levenberg-Marquardt Algorithm in conjunction with the microstructural damage evolution proxies. The presented technique is applicable to electronic assemblies which have been deployed on one thermal environment, then withdrawn from service and targeted for redeployment in a different thermal environment. Test cases have been presented to demonstrate the viability of the technique for assessment of prior damage, operational readiness and residual life for assemblies exposed to multiple thermo-mechanical environments. Prognosticated prior damage and the residual life show good correlation with experimental data, demonstrating the validity of the presented technique for multiple thermo-mechanical environments.

Physics of Failure Based Virtual Testing of Communications Hardware

Communications hardware for high reliability systems are starting to include modern low profile parts such as Quad Flat Pack No-lead (QFN) and Land Grid Array (LGA) packages to take advantage of their size and weight. In these parts, heat sinks often provide a conductive thermal dissipation path. Printed circuit assemblies with these parts will still need to meet the industry specific qualification requirements for thermal and vibration testing. It is beneficial to identify if the equipment will be able to meet the qualification test requirements during the design phase particularly when new technology insertions are being made. In this design, various surface mount packages like LGAs, QFNs and so on were used in a printed circuit board which included two stiffening layers with non-standard laminates. calcePWA is a simulation software which estimates the cycles to failure of components under various loading conditions using Physics of Failure (PoF). The cycles to failure simulation of this design using calcePWA software identified the critical interconnects that are at risk for failure under non-operational test conditions. The design was also evaluated under a long haul aircraft profile, with the assembly in operational state. In operational state simulation, the effectiveness of thermal shunts in reducing board to component thermal differentials was evaluated. Effects of degradations of the thermal shunts with time were used in the evaluation. Results showed that the vibration and shock reliability were less of a concern than thermal cycling for this board layout. Risk mitigation methods for thermal cycling durability were identified and recommended to be used in the system redesign.

F-22 Lessons Learned: Line Replaceable Module (LRM) Electrical Connector—An Investigation of Vibration-Induced Contact Wear and Electro Static Discharge Hardening

Flight Line Replaceable Modules (LRMs) are the foundation for modern day architectures in fighters such as the F-22. The 2-level maintenance concept (flight line to depot) reduces costs for spares and base level repair of circuit cards. However, this maintenance concept is predicated on the ability of the software to isolate failures down to the LRM or circuit card level. The types of failures that result from worn and corroded connectors result in large ambiguity groups; thus, making isolation to the circuit card level difficult. The vibration, thermal, humidity and corrosion environments of the F-22 are severe. Similarly, the ESD environment (for F-22 flight line maintenance) is severe because maintenance is performed without grounding straps or any special handling requirements. Hardware designed for use in this environment must be easily installed, capable of performing in a severe environment while maintaining high data rates without interruption. This paper identifies the F-22 risk reduction approach taken to mitigate the effects of the severe environments. The design & analytical approach taken during the program development phase offers important insight into the methods needed for predicting and analyzing hardware installation within the severe vibration and thermal environments commonly found in today’s fighter aircraft.