Fabrication of Sub-Micron Silicon Vias by Deep Reactive Ion Etching

Advances in Electronic Packaging, Parts A, B, and C ◽

10.1115/ipack2005-73299 ◽

2005 ◽

Author(s):

Shawn X. D. Zhang ◽

Ronald Hon ◽

S. W. Ricky Lee

Keyword(s):

Aspect Ratio ◽

Mechanical System ◽

Reactive Ion Etching ◽

Micro Electro Mechanical System ◽

Experimental Results ◽

Mems Devices ◽

Ion Etching ◽

Deep Reactive Ion Etching ◽

3D Packaging ◽

Silicon Vias

Deep reactive ion etching (DRIE) is a major microfabrication process for micro-electro-mechanical system (MEMS) devices. In recent years DRIE is also applied to make through-silicon-vias (TSVs) for 3D packaging. Typical DRIE-formed TSVs are in the range of a few microns to tens of microns. In the present study, silicon vias with diameters in the sub-micron range (0.5 μm and 0.8 μm) are attempted. For comparison purposes, larger silicon vias (1 μm and 3 μm) are fabricated as well. In this paper, the microfabrication processes are described. The experimental results and comparisons in terms of via uniformity, aspect ratio dependent etching, undercutting, and effects of various mask materials are discussed in detail.

Download Full-text

Deep reactive ion etching of sub-micrometer trenches with ultra high aspect ratio

Microelectronic Engineering ◽

10.1016/j.mee.2013.06.010 ◽

2014 ◽

Vol 113 ◽

pp. 35-39 ◽

Cited By ~ 36

Author(s):

Jayalakshmi Parasuraman ◽

Anand Summanwar ◽

Frédéric Marty ◽

Philippe Basset ◽

Dan E. Angelescu ◽

...

Keyword(s):

Aspect Ratio ◽

High Aspect Ratio ◽

Reactive Ion Etching ◽

Ion Etching ◽

Deep Reactive Ion Etching

Download Full-text

TSV Resist and Residue Removal

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2011dpc-wp14 ◽

2011 ◽

Vol 2011 (DPC) ◽

pp. 001596-001620

Author(s):

Laura Mauer ◽

John Taddei ◽

Ramey Youssef ◽

Kimberly Pollard ◽

Allison Rector

Keyword(s):

Reactive Ion Etching ◽

3D Integration ◽

Auger Analysis ◽

Ion Etching ◽

Deep Reactive Ion Etching ◽

Spray Process ◽

Residue Removal ◽

One Step ◽

Silicon Vias ◽

Etch Residue

3D integration is the most active methodology for increasing device performance. The ability to create Through Silicon Vias (TSV) provides the shortest path for interconnections and will result in increased device speed and reduced package footprint. There are numerous technical papers and presentations on the etching and filling of these vias, however the process for cleaning is seldom mentioned. Historically, after reactive ion etching (RIE), cleaning is accomplished using an ashing process to remove any remaining photoresist, followed by dipping the wafer in a solution-based post etch residue remover. However, in the case of TSV formation, deep reactive ion etching (DRIE) is used to create the vias. A byproduct of this etching process is the formation of a fluorinated passivation layer, often referred to as a fluoropolymer. The fluoropolymer is not easily removed using traditional post etch residue removers, thus creating the opportunity for new and improved formulations and processes for its removal. This paper will describe a robust cleaning process for one step removal of both the photoresist and sidewall polymer residues from TSVs. A combination soak and high pressure spray process using Dynastrip™ AP7880™-C, coupled with a megasonic final rinse provides clean results for high aspect ratio vias. SEM, EDX and Auger analysis will illustrate the cleanliness levels achieved.

Download Full-text

Formation of Through-Silicon-Vias by Laser Drilling and Deep Reactive Ion Etching

Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology ◽

10.1115/imece2004-62322 ◽

2004 ◽

Author(s):

Ronald Hon ◽

Shawn X. D. Zhang ◽

S. W. Ricky Lee

Keyword(s):

Reactive Ion Etching ◽

Three Dimensional ◽

Laser Drilling ◽

Wet Etching ◽

Ion Etching ◽

Through Silicon Vias ◽

Deep Reactive Ion Etching ◽

Definition Of ◽

Silicon Vias ◽

Wafer Thinning

The focus of this study is on the fabrication of through silicon vias (TSV) for three dimensional packaging. According to IPC-6016, the definition of microvias is a hole with a diameter of less than or equal to 150 μm. In order to meet this requirement, laser drilling and deep reactive ion etching (but not wet etching) are used to make the microvias. Comparisons between these two different methods are carried out in terms of wall straightness, smoothness, smallest via produced and time needed for fabrication. In addition, discussion on wafer thinning for making through silicon microvias is given as well.

Download Full-text