Three list scheduling temporal partitioning algorithm of time space characteristic analysis and compare for dynamic reconfigurable computing

2013 ◽  
Author(s):  
Naijin Chen
Keyword(s):  
Reconfigurable Computing ◽  
List Scheduling ◽  
Characteristic Analysis ◽  
Temporal Partitioning ◽  
Time Space ◽  
Space Characteristic ◽  
Partitioning Algorithm

scholarly journals The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

2021 ◽  
Author(s):  
Valeri Kirischian
Keyword(s):  
Reconfigurable Computing ◽  
Cost Effective ◽  
Design Synthesis ◽  
Temporal Partitioning ◽  
Cad System ◽  
Run Time ◽  
Hardware Faults ◽  
Parametric Constraint ◽  
High Level ◽  
Task Segmentation

The main motivation factors for the proposed research were the increase of cost-efficiency of FPGA based systems and the simplification of the design process. The first factor is optimization of design in multi-parametric constraint space. The second factor is the design of reconfigurable systems based on higher level of abstraction in a form of macro-functions rather than conventional HDL primitives. Main goal of this work was to create a methodology for automated cost-effective design synthesis of FPGA systems by utilizing temporal partitioning concept. Temporal partitioning provides powerful mechanism that allows to design cost-effective multi-parametrically optimized architectures. Another feature of these architectures is the ability for run-time self-restoration from hardware faults. As the result of the proposed research this methodology was created and successfully verified on the first prototype of Multi-mode Adaptive Reconfigurable System (MARS) with embedded Temporal Partitioning Mechanism (TPM). A special CAD software system was developed for automated application programming, automated task segmentation, and further high-level synthesis of segment specific processors (SSPs). Several novel methodologies were proposed, developed, and verified including: a methodology for creation of macro-operators (MOs) and associated set of optimized virtual hardware components (VHCs); an automated task segmentation methodology and synthesis of segment specific processors from the VHCs; methodology for integration of fault tolerance mechanisms with the self-restoration capability. The latter mechanism made possible the mitigation of transient and permanent hardware faults in run-time. The proof-of-concept component of this research consists of implementation of the above methodologies and mechanisms in the special software CAD system and verification on the experimental setup based on the prototype of system with TPM (MARS platform). As the result, all the developed methodologies and architectural solutions were tested and their effectiveness was demonstrated.

scholarly journals Temporal niche partitioning as a novel mechanism promoting co-existence of sympatric predators in marine systems

2021 ◽  
Vol 288 (1954) ◽  
pp. 20210816
Author(s):  
Karissa O. Lear ◽  
Nicholas M. Whitney ◽  
John J. Morris ◽  
Adrian C. Gleiss
Keyword(s):  
Activity Patterns ◽  
Interference Competition ◽  
Niche Partitioning ◽  
Common Mechanism ◽  
Multiple Predators ◽  
Temporal Partitioning ◽  
Marine Systems ◽  
Temporal Niche ◽  
Time Space ◽  
Sensory Adaptations

Niche partitioning of time, space or resources is considered the key to allowing the coexistence of competitor species, and particularly guilds of predators. However, the extent to which these processes occur in marine systems is poorly understood due to the difficulty in studying fine-scale movements and activity patterns in mobile underwater species. Here, we used acceleration data-loggers to investigate temporal partitioning in a guild of marine predators. Six species of co-occurring large coastal sharks demonstrated distinct diel patterns of activity, providing evidence of strong temporal partitioning of foraging times. This is the first instance of diel temporal niche partitioning described in a marine predator guild, and is probably driven by a combination of physiological constraints in diel timing of activity (e.g. sensory adaptations) and interference competition (hierarchical predation within the guild), which may force less dominant predators to suboptimal foraging times to avoid agonistic interactions. Temporal partitioning is often thought to be rare compared to other partitioning mechanisms, but the occurrence of temporal partitioning here and similar characteristics in many other marine ecosystems (multiple predators simultaneously present in the same space with dietary overlap) introduces the question of whether this is a common mechanism of resource division in marine systems.

scholarly journals Time-space Characteristic of Interruptible Load on Dispatch Solution

2015 ◽  
Vol 48 (28) ◽  
pp. 1355-1358
Author(s):  
Shuangchen Yao ◽  
Haoming Liu ◽  
Dan Lu ◽  
Xiaoling Yuan
Keyword(s):  
Interruptible Load ◽  
Time Space ◽  
Space Characteristic

scholarly journals Traffic Crash Evolution Characteristic Analysis and Spatiotemporal Hotspot Identification of Urban Road Intersections

2018 ◽  
Vol 11 (1) ◽  
pp. 160 ◽  
Author(s):  
Zeyang Cheng ◽  
Zhenshan Zu ◽  
Jian Lu
Keyword(s):  
Road Traffic ◽  
Hot Spot ◽  
Statistical Significance ◽  
Characteristic Analysis ◽  
Traffic Crashes ◽  
Traffic Crash ◽  
Road Traffic Safety ◽  
Time Space ◽  
Road Intersections ◽  
Crash Hotspots

Road traffic safety is a key concern of transport management as it has severely restricted Chinese economic and social development. With the objective to prevent and reduce road traffic crashes, this study proposes a comprehensive spatiotemporal analysis method that integrates the time-space cube analysis, spatial autocorrelation analysis, and emerging hot spot analysis for exploring the traffic crash evolution characteristics and identifying crash hot spots. These analyses are all conducted by the corresponding toolbox of ArcGIS 10.5. Then, a small sized-city of China (i.e., Wujiang) is selected as the case study, and the historical traffic crash data occurring at the road intersections of Wujiang for the year 2016 are analyzed by the proposed method. The analysis process identifies the high incidence locations of traffic crashes, then presents the spatial change trend and statistical significance of the crash locations. Finally, different types of crash hotspots, as well as their evolution patterns over time, are determined. The results illustrate that the traffic crash hotspots of road intersections are primarily distributed in the Northeast area of Wujiang’s major urban area, while the crash cold spots are concentrated in the Southwest of Wujiang, which points out the direction for crash prevention. In addition, the finding has a potential engineering application value, and it is of great significance to the sustainable development of Wujiang.

The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

2021 ◽  
Author(s):  
Valeri Kirischian
Keyword(s):  
Reconfigurable Computing ◽  
Cost Effective ◽  
Design Synthesis ◽  
Temporal Partitioning ◽  
Cad System ◽  
Run Time ◽  
Hardware Faults ◽  
Parametric Constraint ◽  
High Level ◽  
Task Segmentation

The main motivation factors for the proposed research were the increase of cost-efficiency of FPGA based systems and the simplification of the design process. The first factor is optimization of design in multi-parametric constraint space. The second factor is the design of reconfigurable systems based on higher level of abstraction in a form of macro-functions rather than conventional HDL primitives. Main goal of this work was to create a methodology for automated cost-effective design synthesis of FPGA systems by utilizing temporal partitioning concept. Temporal partitioning provides powerful mechanism that allows to design cost-effective multi-parametrically optimized architectures. Another feature of these architectures is the ability for run-time self-restoration from hardware faults. As the result of the proposed research this methodology was created and successfully verified on the first prototype of Multi-mode Adaptive Reconfigurable System (MARS) with embedded Temporal Partitioning Mechanism (TPM). A special CAD software system was developed for automated application programming, automated task segmentation, and further high-level synthesis of segment specific processors (SSPs). Several novel methodologies were proposed, developed, and verified including: a methodology for creation of macro-operators (MOs) and associated set of optimized virtual hardware components (VHCs); an automated task segmentation methodology and synthesis of segment specific processors from the VHCs; methodology for integration of fault tolerance mechanisms with the self-restoration capability. The latter mechanism made possible the mitigation of transient and permanent hardware faults in run-time. The proof-of-concept component of this research consists of implementation of the above methodologies and mechanisms in the special software CAD system and verification on the experimental setup based on the prototype of system with TPM (MARS platform). As the result, all the developed methodologies and architectural solutions were tested and their effectiveness was demonstrated.

scholarly journals FPGA based computing platform with temporal partitioning mechanism

2021 ◽  
Author(s):  
Valeri Kirischian
Keyword(s):  
Flash Memory ◽  
Reconfigurable Computing ◽  
Temporal Partitioning ◽  
Computing Platform ◽  
Field Programmable ◽  
Run Time ◽  
Reconfigurable Platform ◽  
Algorithm And Data Structure ◽  
Run Time Reconfiguration ◽  
Optimal Adaptation

In the presented work the FPGA based run-time reconfigurable platform with temporal partitioning of hardware resources is proposed. This platform is based on the Field Programmable Gate Array (FPGA) device that can be reconfigured "on-fly" to provide the optimal adaptation of a processing architecture to the algorithm and data structure by utilization of developed mechanisms of temporal partitioning of computational / logic resources. It was shown that the proposed approach allows reaching very high cost-effectiveness of the computing platform oriented on processing of framed data-streams. On the other hand, the hardware programming and compilation processes could be simplified by utilization of library of precompiled Virtual Hardware Components stored in the on-board FLASH memory. Paper presents theoretical proof of the proposed approach by analytical comparison of the performance that could be reached on the conventional processors and FPGA platform with Temporal Partitioning Mechanism (TPM) of hardware resources. The implementation of the proposed TPM on the basis of Xilinx Spartan-3 and Xilinx Virtex II FPGA devices is described. Experimental results gained on the prototype of the FPGA based platform with TPM are discussed and analyzed. Keywords: reconfigurable computing, data-stream processing, FPGA, run-time reconfiguration, temporal partitioning.

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