scholarly journals FPGA based computing platform with temporal partitioning mechanism

2021 ◽  
Author(s):  
Valeri Kirischian
Keyword(s):  
Flash Memory ◽  
Reconfigurable Computing ◽  
Temporal Partitioning ◽  
Computing Platform ◽  
Field Programmable ◽  
Run Time ◽  
Reconfigurable Platform ◽  
Algorithm And Data Structure ◽  
Run Time Reconfiguration ◽  
Optimal Adaptation

In the presented work the FPGA based run-time reconfigurable platform with temporal partitioning of hardware resources is proposed. This platform is based on the Field Programmable Gate Array (FPGA) device that can be reconfigured "on-fly" to provide the optimal adaptation of a processing architecture to the algorithm and data structure by utilization of developed mechanisms of temporal partitioning of computational / logic resources. It was shown that the proposed approach allows reaching very high cost-effectiveness of the computing platform oriented on processing of framed data-streams. On the other hand, the hardware programming and compilation processes could be simplified by utilization of library of precompiled Virtual Hardware Components stored in the on-board FLASH memory. Paper presents theoretical proof of the proposed approach by analytical comparison of the performance that could be reached on the conventional processors and FPGA platform with Temporal Partitioning Mechanism (TPM) of hardware resources. The implementation of the proposed TPM on the basis of Xilinx Spartan-3 and Xilinx Virtex II FPGA devices is described. Experimental results gained on the prototype of the FPGA based platform with TPM are discussed and analyzed. Keywords: reconfigurable computing, data-stream processing, FPGA, run-time reconfiguration, temporal partitioning.

scholarly journals FPGA based computing platform with temporal partitioning mechanism

2021 ◽  
Author(s):  
Valeri Kirischian
Keyword(s):  
Flash Memory ◽  
Reconfigurable Computing ◽  
Temporal Partitioning ◽  
Computing Platform ◽  
Field Programmable ◽  
Run Time ◽  
Reconfigurable Platform ◽  
Algorithm And Data Structure ◽  
Run Time Reconfiguration ◽  
Optimal Adaptation

In the presented work the FPGA based run-time reconfigurable platform with temporal partitioning of hardware resources is proposed. This platform is based on the Field Programmable Gate Array (FPGA) device that can be reconfigured "on-fly" to provide the optimal adaptation of a processing architecture to the algorithm and data structure by utilization of developed mechanisms of temporal partitioning of computational / logic resources. It was shown that the proposed approach allows reaching very high cost-effectiveness of the computing platform oriented on processing of framed data-streams. On the other hand, the hardware programming and compilation processes could be simplified by utilization of library of precompiled Virtual Hardware Components stored in the on-board FLASH memory. Paper presents theoretical proof of the proposed approach by analytical comparison of the performance that could be reached on the conventional processors and FPGA platform with Temporal Partitioning Mechanism (TPM) of hardware resources. The implementation of the proposed TPM on the basis of Xilinx Spartan-3 and Xilinx Virtex II FPGA devices is described. Experimental results gained on the prototype of the FPGA based platform with TPM are discussed and analyzed. Keywords: reconfigurable computing, data-stream processing, FPGA, run-time reconfiguration, temporal partitioning.

scholarly journals AC_ICAP: A Flexible High Speed ICAP Controller

2015 ◽  
Vol 2015 ◽  
pp. 1-15 ◽  
Author(s):  
Luis Andres Cardona ◽  
Carles Ferrer
Keyword(s):  
High Speed ◽  
Access Port ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Speed Up ◽  
Run Time ◽  
Ip Cores ◽  
Similar Solutions ◽  
Internal Configuration ◽  
Run Time Reconfiguration

The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC_ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution to provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were implemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI interfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage of the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAs. Results of reconfiguration time showed that run-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5 μs which implies a speed-up of more than 380x compared to the Xilinx XPS_HWICAP controller.

scholarly journals The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

2021 ◽  
Author(s):  
Valeri Kirischian
Keyword(s):  
Reconfigurable Computing ◽  
Cost Effective ◽  
Design Synthesis ◽  
Temporal Partitioning ◽  
Cad System ◽  
Run Time ◽  
Hardware Faults ◽  
Parametric Constraint ◽  
High Level ◽  
Task Segmentation

The main motivation factors for the proposed research were the increase of cost-efficiency of FPGA based systems and the simplification of the design process. The first factor is optimization of design in multi-parametric constraint space. The second factor is the design of reconfigurable systems based on higher level of abstraction in a form of macro-functions rather than conventional HDL primitives. Main goal of this work was to create a methodology for automated cost-effective design synthesis of FPGA systems by utilizing temporal partitioning concept. Temporal partitioning provides powerful mechanism that allows to design cost-effective multi-parametrically optimized architectures. Another feature of these architectures is the ability for run-time self-restoration from hardware faults. As the result of the proposed research this methodology was created and successfully verified on the first prototype of Multi-mode Adaptive Reconfigurable System (MARS) with embedded Temporal Partitioning Mechanism (TPM). A special CAD software system was developed for automated application programming, automated task segmentation, and further high-level synthesis of segment specific processors (SSPs). Several novel methodologies were proposed, developed, and verified including: a methodology for creation of macro-operators (MOs) and associated set of optimized virtual hardware components (VHCs); an automated task segmentation methodology and synthesis of segment specific processors from the VHCs; methodology for integration of fault tolerance mechanisms with the self-restoration capability. The latter mechanism made possible the mitigation of transient and permanent hardware faults in run-time. The proof-of-concept component of this research consists of implementation of the above methodologies and mechanisms in the special software CAD system and verification on the experimental setup based on the prototype of system with TPM (MARS platform). As the result, all the developed methodologies and architectural solutions were tested and their effectiveness was demonstrated.

scholarly journals Self-Restoration Mechanism for Run-Time Reconfigurable Data-Stream Processors

2021 ◽  
Author(s):  
Irina Terterian
Keyword(s):  
Reconfigurable Computing ◽  
High Performance ◽  
Processing System ◽  
Maximum Level ◽  
Computing Systems ◽  
Computing Platform ◽  
Restoration Mechanism ◽  
Run Time ◽  
Computing Platforms ◽  
The Cost

The cost of a hardward failure in high-performance computing systems is usually extremely high because of the system stall where billions of operations can be lost within one second. Thus, implementation of self-restoration mechanisms is one of the most effective approaches to keep system performance on a required level. The project presents a new approach, which allows retaining the performance of the Run-Time Reconfigurable stream processing system on its maximum level. This becomes possible by development of multi-level self-restoration mechanism that consists of: restoration by FPGA-scrubbing, restoration by FPGA-slot replacement and restoration with optimum performance degradation. All above levels of restoration procedure were developed and tested on reconfigurable computing platform based on XILINX Virtex FPGA. Analysis of achieved results of the developed mechanism shows a very fast restoration of functionality and dramatic increase of lifetime of FPGA based computing platforms.

scholarly journals Self-Restoration Mechanism for Run-Time Reconfigurable Data-Stream Processors

2021 ◽  
Author(s):  
Irina Terterian
Keyword(s):  
Reconfigurable Computing ◽  
High Performance ◽  
Processing System ◽  
Maximum Level ◽  
Computing Systems ◽  
Computing Platform ◽  
Restoration Mechanism ◽  
Run Time ◽  
Computing Platforms ◽  
The Cost

The cost of a hardward failure in high-performance computing systems is usually extremely high because of the system stall where billions of operations can be lost within one second. Thus, implementation of self-restoration mechanisms is one of the most effective approaches to keep system performance on a required level. The project presents a new approach, which allows retaining the performance of the Run-Time Reconfigurable stream processing system on its maximum level. This becomes possible by development of multi-level self-restoration mechanism that consists of: restoration by FPGA-scrubbing, restoration by FPGA-slot replacement and restoration with optimum performance degradation. All above levels of restoration procedure were developed and tested on reconfigurable computing platform based on XILINX Virtex FPGA. Analysis of achieved results of the developed mechanism shows a very fast restoration of functionality and dramatic increase of lifetime of FPGA based computing platforms.

The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

2021 ◽  
Author(s):  
Valeri Kirischian
Keyword(s):  
Reconfigurable Computing ◽  
Cost Effective ◽  
Design Synthesis ◽  
Temporal Partitioning ◽  
Cad System ◽  
Run Time ◽  
Hardware Faults ◽  
Parametric Constraint ◽  
High Level ◽  
Task Segmentation

The main motivation factors for the proposed research were the increase of cost-efficiency of FPGA based systems and the simplification of the design process. The first factor is optimization of design in multi-parametric constraint space. The second factor is the design of reconfigurable systems based on higher level of abstraction in a form of macro-functions rather than conventional HDL primitives. Main goal of this work was to create a methodology for automated cost-effective design synthesis of FPGA systems by utilizing temporal partitioning concept. Temporal partitioning provides powerful mechanism that allows to design cost-effective multi-parametrically optimized architectures. Another feature of these architectures is the ability for run-time self-restoration from hardware faults. As the result of the proposed research this methodology was created and successfully verified on the first prototype of Multi-mode Adaptive Reconfigurable System (MARS) with embedded Temporal Partitioning Mechanism (TPM). A special CAD software system was developed for automated application programming, automated task segmentation, and further high-level synthesis of segment specific processors (SSPs). Several novel methodologies were proposed, developed, and verified including: a methodology for creation of macro-operators (MOs) and associated set of optimized virtual hardware components (VHCs); an automated task segmentation methodology and synthesis of segment specific processors from the VHCs; methodology for integration of fault tolerance mechanisms with the self-restoration capability. The latter mechanism made possible the mitigation of transient and permanent hardware faults in run-time. The proof-of-concept component of this research consists of implementation of the above methodologies and mechanisms in the special software CAD system and verification on the experimental setup based on the prototype of system with TPM (MARS platform). As the result, all the developed methodologies and architectural solutions were tested and their effectiveness was demonstrated.

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