A high-speed driver for silicon photonics Mach-Zehnder modulator for high data-rate transfer of particle collision images in high-energy physics and in medical physics

2018 ◽  
Author(s):  
Sergio Saponara ◽  
Guido Magazzu ◽  
Gabriele Ciarpi
Keyword(s):  
Silicon Photonics ◽  
High Speed ◽  
High Energy Physics ◽  
Medical Physics ◽  
High Energy ◽  
High Data Rate ◽  
Particle Collision ◽  
High Data ◽  
Mach Zehnder Modulator ◽  
Energy Physics

scholarly journals Design and Performance Evaluation of Multi-Gb/s Silicon Photonics Transmitters for High Energy Physics

Energies ◽  
2020 ◽  
Vol 13 (14) ◽  
pp. 3569
Author(s):  
Simone Cammarata ◽  
Gabriele Ciarpi ◽  
Stefano Faralli ◽  
Philippe Velha ◽  
Guido Magazzù ◽  
...  
Keyword(s):  
Silicon Photonics ◽  
Particle Physics ◽  
High Energy Physics ◽  
Current Mode ◽  
High Energy ◽  
Silicon On Insulator ◽  
Output Stage ◽  
Optical Links ◽  
And Performance ◽  
Energy Physics

Optical links are rapidly becoming pervasive in the readout chains of particle physics detector systems. Silicon photonics (SiPh) stands as an attractive candidate to sustain the radiation levels foreseen in the next-generation experiments, while guaranteeing, at the same time, multi-Gb/s and energy-efficient data transmission. Integrated electronic drivers are needed to enable SiPh modulators’ deployment in compact on-detector front-end modules. A current-mode logic-based driver harnessing a pseudo-differential output stage is proposed in this work to drive different types of SiPh devices by means of the same circuit topology. The proposed driver, realized in a 65 nm bulk technology and already tested to behave properly up to an 8 MGy total ionizing dose, is hybridly integrated in this work with a lumped-element Mach–Zehnder modulator (MZM) and a ring modulator (RM), both fabricated in a 130 nm silicon-on-insulator (SOI) process. Bit-error-rate (BER) performances confirm the applicability of the selected architecture to either differential and single-ended loads. A 5 Gb/s data rate, in line with the current high energy physics requirements, is achieved in the RM case, while a packaging-related performance degradation is captured in the MZM-based system, confirming the importance of interconnection modeling.

scholarly journals Hardware Implementation Study of Particle Tracking Algorithm on FPGAs

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2546
Author(s):  
Alessandro Gabrielli ◽  
Fabrizio Alfonsi ◽  
Alberto Annovi ◽  
Alessandra Camplani ◽  
Alessandro Cerri
Keyword(s):  
High Speed ◽  
High Performance ◽  
Hardware Implementation ◽  
High Energy Physics ◽  
Medical Image Analysis ◽  
Computation Time ◽  
High Energy ◽  
Spatial Transformation ◽  
Flip Flop ◽  
Energy Physics

In recent years, the technological node used to implement FPGA devices has led to very high performance in terms of computational capacity and in some applications these can be much more efficient than CPUs or other programmable devices. The clock managers and the enormous versatility of communication technology through digital transceivers place FPGAs in a prime position for many applications. For example, from real-time medical image analysis to high energy physics particle trajectory recognition, where computation time can be crucial, the benefits of using frontier FPGA capabilities are even more relevant. This paper shows an example of FPGA hardware implementation, via a firmware design, of a complex analytical algorithm: The Hough transform. This is a mathematical spatial transformation used here to facilitate on-the-fly recognition of the trajectories of ionising particles as they pass through the so-called tracker apparatus within high-energy physics detectors. This is a general study to demonstrate that this technique is not only implementable via software-based systems, but can also be exploited using consumer hardware devices. In this context the latter are known as hardware accelerators. In this article in particular, the Xilinx UltraScale+ FPGA is investigated as it belongs to one of the frontier family devices on the market. These FPGAs make it possible to reach high-speed clock frequencies at the expense of acceptable energy consumption thanks to the 14 nm technological node used by the vendor. These devices feature a huge number of gates, high-bandwidth memories, transceivers and other high-performance electronics in a single chip, enabling the design of large, complex and scalable architectures. In particular the Xilinx Alveo U250 has been investigated. A target frequency of 250 MHz and a total latency of 30 clock periods have been achieved using only the 17 ÷ 53% of LUTs, the 8 ÷ 12% of DSPs, the 1 ÷ 3% of Block Rams and a Flip Flop occupancy range of 9 ÷ 28%.

KEKNET, a high speed on-line network for high energy physics

1979 ◽  
Vol 159 (1) ◽  
pp. 7-19 ◽  
Author(s):  
Y. Asano ◽  
S. Inaba ◽  
S. Kabe ◽  
A. Kaise ◽  
Y. Karita ◽  
...  
Keyword(s):  
High Speed ◽  
High Energy Physics ◽  
High Energy ◽  
On Line ◽  
Line Network ◽  
Energy Physics
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