Line-edge roughness reduction for advanced metal gate etch with 193-nm lithography in a silicon decoupled plasma source etcher (DPSII)

2003 ◽  
Author(s):  
Tito Chowdhury ◽  
Hanna Bamnolker ◽  
Roni Khen ◽  
Chan-Lon Yang ◽  
Hean-Cheal Lee ◽  
...  
Keyword(s):  
Plasma Source ◽  
Line Edge Roughness ◽  
Metal Gate ◽  
Edge Roughness ◽  
193 Nm

Study of the fundamental contributions to line edge roughness in a 193 nm, top surface imaging system

2000 ◽  
Vol 18 (5) ◽  
pp. 2551 ◽  
Author(s):  
Mark H. Somervell ◽  
David S. Fryer ◽  
Brian Osborn ◽  
Kyle Patterson ◽  
Jeffrey Byers ◽  
...  
Keyword(s):  
Imaging System ◽  
Surface Imaging ◽  
Line Edge Roughness ◽  
Edge Roughness ◽  
Top Surface Imaging ◽  
193 Nm

Impact of Fin Line Edge Roughness and Metal Gate Granularity on Variability of 10-nm Node SOI n-FinFET

2019 ◽  
Vol 66 (11) ◽  
pp. 4646-4652 ◽  
Author(s):  
Akhil Sudarsanan ◽  
Sankatali Venkateswarlu ◽  
Kaushik Nayak
Keyword(s):  
Line Edge Roughness ◽  
Metal Gate ◽  
Fin Line ◽  
Edge Roughness

CD-SEM measurement line edge roughness test patterns for 193 nm lithography

2003 ◽  
Author(s):  
Benjamin D. Bunday ◽  
Michael Bishop ◽  
John S. Villarrubia ◽  
Andras E. Vladar
Keyword(s):  
Line Edge Roughness ◽  
Edge Roughness ◽  
193 Nm ◽  
Measurement Line

Line-edge roughness in 193-nm resists: lithographic aspects and etch transfer

2007 ◽  
Author(s):  
Thomas Wallow ◽  
Alden Acheta ◽  
Yuansheng Ma ◽  
Adam Pawloski ◽  
Scott Bell ◽  
...  
Keyword(s):  
Line Edge Roughness ◽  
Edge Roughness ◽  
193 Nm

CD-SEM measurement line-edge roughness test patterns for 193-nm lithography

2003 ◽  
Author(s):  
Benjamin D. Bunday ◽  
Michael Bishop ◽  
John S. Villarrubia ◽  
Andras E. Vladar
Keyword(s):  
Line Edge Roughness ◽  
Edge Roughness ◽  
193 Nm ◽  
Measurement Line

Degeneration of Line-Edge Roughness-Induced Variability for Dual-Metal Gate Fin Field-Effect Transistors

2020 ◽  
Vol 15 (1) ◽  
pp. 142-146
Author(s):  
Liang Dai ◽  
Wei-Feng Lü
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Line Edge Roughness ◽  
Metal Gate ◽  
Edge Roughness ◽  
Simulation Results ◽  
Dual Metal ◽  
Aided Design ◽  
First Time

We investigate, for the first time, the effect of line-edge roughness (LER)-induced variability for dual-metal gate (DMG) Fin field-effect transistors (FinFETs) using a computer-aided-design simulation. The Gaussian autocorrelation function is utilized for generating the LER sequence. From the standard deviations of subthreshold swing (SS), threshold voltage (VTH), and transconductance (gm), the simulation results indicate that the LER-induced electrostatic integrity variability is related to the ratio of control gate to total gate lengths. The variability caused by LER degrades with respect to the length of control gate near the source. Our work fills a gap in the study of LER-induced variability for DMG FinFETs, and suggests that the length of the control gate near the source should be greater than or equal to the screen gate near the drain in the entire gate.

Effects of different processing conditions on line-edge roughness for 193-nm and 157-nm resists

2004 ◽  
Author(s):  
Monique Ercken ◽  
Leonardus H. A. Leunissen ◽  
Ivan Pollentier ◽  
George P. Patsis ◽  
Vassilios Constantoudis ◽  
...  
Keyword(s):  
Processing Conditions ◽  
Line Edge Roughness ◽  
Edge Roughness ◽  
On Line ◽  
193 Nm

Rinse additives for line-edge roughness control in 193-nm lithography

2004 ◽  
Author(s):  
Dario L. Goldfarb ◽  
Sean D. Burns ◽  
Ryan L. Burns ◽  
Colin J. Brodsky ◽  
Margaret C. Lawson ◽  
...  
Keyword(s):  
Line Edge Roughness ◽  
Edge Roughness ◽  
Roughness Control ◽  
193 Nm

Characterization of Line-Edge Roughness in Cu/Low-kInterconnect Pattern

2008 ◽  
Vol 47 (4) ◽  
pp. 2501-2505 ◽  
Author(s):  
Atsuko Yamaguchi ◽  
Daisuke Ryuzaki ◽  
Ken-ichi Takeda ◽  
Jiro Yamamoto ◽  
Hiroki Kawada ◽  
...  
Keyword(s):  
Line Edge Roughness ◽  
Edge Roughness
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