Impact of Fin Line Edge Roughness and Metal Gate Granularity on Variability of 10-nm Node SOI n-FinFET

2019 ◽  
Vol 66 (11) ◽  
pp. 4646-4652 ◽  
Author(s):  
Akhil Sudarsanan ◽  
Sankatali Venkateswarlu ◽  
Kaushik Nayak
2003 ◽  
Author(s):  
Tito Chowdhury ◽  
Hanna Bamnolker ◽  
Roni Khen ◽  
Chan-Lon Yang ◽  
Hean-Cheal Lee ◽  
...  

2020 ◽  
Vol 15 (1) ◽  
pp. 142-146
Author(s):  
Liang Dai ◽  
Wei-Feng Lü

We investigate, for the first time, the effect of line-edge roughness (LER)-induced variability for dual-metal gate (DMG) Fin field-effect transistors (FinFETs) using a computer-aided-design simulation. The Gaussian autocorrelation function is utilized for generating the LER sequence. From the standard deviations of subthreshold swing (SS), threshold voltage (VTH), and transconductance (gm), the simulation results indicate that the LER-induced electrostatic integrity variability is related to the ratio of control gate to total gate lengths. The variability caused by LER degrades with respect to the length of control gate near the source. Our work fills a gap in the study of LER-induced variability for DMG FinFETs, and suggests that the length of the control gate near the source should be greater than or equal to the screen gate near the drain in the entire gate.


2008 ◽  
Vol 47 (4) ◽  
pp. 2501-2505 ◽  
Author(s):  
Atsuko Yamaguchi ◽  
Daisuke Ryuzaki ◽  
Ken-ichi Takeda ◽  
Jiro Yamamoto ◽  
Hiroki Kawada ◽  
...  

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