Bipolar device technology challenge and opportunity

1985 ◽  
Vol 63 (6) ◽  
pp. 683-692 ◽  
Author(s):  
H. D. Barber
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Chemical Vapor ◽  
Low Noise ◽  
Isolation Techniques ◽  
Propagation Delays ◽  
Technological Barriers ◽  
On Chip ◽  
Bipolar Device

Silicon bipolar device technologies provided 65% of the world's integrated circuits in 1983. Where low noise, high current, low or high voltage, high speed or low cost are required, bipolar technologies are used. This paper will review the present status of bipolar device technologies, which make possible 100-ps gate-propagation delays, 150-μm2 gate areas, 1-GHz bandwidth amplifiers, on-chip control of over 1-A, 350-V operation, 14-GHz fT's and 10-ns. analogue-to-8-bit digital conversion. These devices are realized because of advances in isolation techniques, chemical-vapor deposition, photolithography, diffusion, ion implantation, conductor–contact interconnection technology, etching processes, and materials preparation. This paper will discuss some of the fundamental problems, modelling difficulties, and technological barriers that will impact the future development of bipolar integrated circuits.

scholarly journals A 1GHz Low-cost, Ultra Low-noise Preamplifier

2020 ◽  
Vol 11 ◽  
pp. 120-126
Author(s):  
J. Chatzakis ◽  
S. Hassan ◽  
E. Clark ◽  
M. Tatarakis
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Low Noise ◽  
Silicon Photomultipliers ◽  
Low Frequencies ◽  
Measurement Systems ◽  
Speed Measurement ◽  
Ultra Low Noise ◽  
Low Noise Preamplifier

A high quality, compact 1GHz preamplifier suitable for operation in conjunction with micro channelplates (MCP) and silicon Photomultipliers (SiPM), that is comprised of two integrated circuits is described inthis paper. The amplifier requires no adjustment and has a flat response from low frequencies and adequatebandwidth for high speed measurement systems.

scholarly journals In-Plane Monolithic Integration of Scaled III-V Photonic Devices

2021 ◽  
Vol 11 (4) ◽  
pp. 1887
Author(s):  
Markus Scherrer ◽  
Noelia Vico Triviño ◽  
Svenja Mauthe ◽  
Preksha Tiwari ◽  
Heinz Schmid ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Photonic Devices ◽  
Monolithic Integration ◽  
Light Emitters ◽  
Fully Integrated ◽  
Large Lattice ◽  
Hybrid Iii ◽  
Gain Material

It is a long-standing goal to leverage silicon photonics through the combination of a low-cost advanced silicon platform with III-V-based active gain material. The monolithic integration of the III-V material is ultimately desirable for scalable integrated circuits but inherently challenging due to the large lattice and thermal mismatch with Si. Here, we briefly review different approaches to monolithic III-V integration while focusing on discussing the results achieved using an integration technique called template-assisted selective epitaxy (TASE), which provides some unique opportunities compared to existing state-of-the-art approaches. This method relies on the selective replacement of a prepatterned silicon structure with III-V material and thereby achieves the self-aligned in-plane monolithic integration of III-Vs on silicon. In our group, we have realized several embodiments of TASE for different applications; here, we will focus specifically on in-plane integrated photonic structures due to the ease with which these can be coupled to SOI waveguides and the inherent in-plane doping orientation, which is beneficial to waveguide-coupled architectures. In particular, we will discuss light emitters based on hybrid III-V/Si photonic crystal structures and high-speed InGaAs detectors, both covering the entire telecom wavelength spectral range. This opens a new path towards the realization of fully integrated, densely packed, and scalable photonic integrated circuits.

scholarly journals Low-cost infrared sensor for wildlife detection in vegetation

2017 ◽  
Vol 63 (Special Issue) ◽  
pp. S13-S17
Author(s):  
Lev Jakub ◽  
Shapoval Vadym ◽  
Bartoška Jan ◽  
Kumhála František
Keyword(s):  
High Speed ◽  
High Probability ◽  
Low Cost ◽  
Low Noise ◽  
Infrared Sensor ◽  
Direct Sunlight ◽  
Infrared Technology ◽  
Wildlife Detection ◽  
Infrared Array ◽  
Very High

The protection of wild animals from mutilation or being killed during haymaking is still a serious problem connected with high working speeds and widths of modern harvesting machines. That is why the main aim of this study was to test low-cost, high-speed and low-noise infrared array sensor Melexis MLX90621 for the application of wildlife detection with the potential to be used in front of the mower equipment. The tests with two different crops with or without a hidden dog were made. Results showed that the sensor is able to detect an animal hidden in the crop with very high probability. Nevertheless, direct sunlight conditions can cause the problems when using infrared technology. A simultaneous use of other sensors working on different principle than infrared technology can be thus recommended.

scholarly journals A Broadband THz On-Chip Transition Using a Dipole Antenna with Integrated Balun

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 236 ◽  
Author(s):  
Wonseok Choe ◽  
Jinho Jeong
Keyword(s):  
Integrated Circuits ◽  
Insertion Loss ◽  
Low Cost ◽  
Three Dimensional ◽  
Equivalent Circuit Model ◽  
Dipole Antenna ◽  
Impedance Match ◽  
Inp Substrate ◽  
On Chip ◽  
High Dielectric

A waveguide-to-microstrip transition is an essential component for packaging integrated circuits (ICs) in rectangular waveguides, especially at millimeter-wave and terahertz (THz) frequencies. At THz frequencies, the on-chip transitions, which are monolithically integrated in ICs are preferred to off-chip transitions, as the former can eliminate the wire-bonding process, which can cause severe impedance mismatch and additional insertion loss of the transitions. Therefore, on-chip transitions can allow the production of low cost and repeatable THz modules. However, on-chip transitions show limited performance in insertion loss and bandwidth, more seriously, this is an in-band resonance issue. These problems are mainly caused by the substrate used in the THz ICs, such as an indium phosphide (InP), which exhibits a high dielectric constant, high dielectric loss, and high thickness, compared with the size of THz waveguides. In this work, we propose a broadband THz on-chip transition using a dipole antenna with an integrated balun in the InP substrate. The transition is designed using three-dimensional electromagnetic (EM) simulations based on the equivalent circuit model. We show that in-band resonances can be induced within the InP substrate and also prove that backside vias can effectively eliminate these resonances. Measurement of the fabricated on-chip transition in 250 nm InP heterojunction bipolar transistor (HBT) technology, shows wideband impedance match and low insertion loss at H-band frequencies (220–320 GHz), without in-band resonances, due to the properly placed backside vias.

Si-Ge heterojunction bipolar technology for high-speed integrated circuits

1996 ◽  
Vol 74 (S1) ◽  
pp. 159-166
Author(s):  
D. C. Ahlgren ◽  
S. J. Jeng ◽  
D. Nguyen-Ngoc ◽  
K. Stein ◽  
D. Sunderland ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Performance ◽  
Full Range ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Voltage Controlled Oscillators ◽  
Sige Hbt ◽  
Trade Offs ◽  
Scale Integration

This review discusses the fundamentals of SiGe epitaxial base heterojunction bipolar transistor (HBT) technology that have been developed for use in analog and mixed-signal applications in the 1–20 GHz range. The basic principles of operation of the graded base SiGe HBT are reviewed. These principles are then used to explore the design optimization for analog applications. Device results are presented that illustrate some important trade-offs in device design. A discussion of the use of UHV/CVD for the deposition of the epitaxial base profile is followed by an overview of the integrated process. This process, which has been installed on 200 mm wafers in IBM's Advanced Semiconductor Technology Center in Hopewell Junction, N.Y., also includes a full range of support devices. The process has demonstrated SiGe HBT performance, reliability, and yield in a CMOS fabrication with the addition of only one tool for UHV/CVD deposition of the epi-base and, with minimal additional process steps, can be used to fabricate full BiCMOS designs. This paper concludes with a discussion of high-performance circuits fabricated to date, including ECL ring'oscillators, power amplifiers, low-noise amplifiers, voltage-controlled oscillators, and finally a 12-bit DAC that features nearly 3000 SiGe HBT devices demonstrating medium-scale integration.

SENSING AND ACTUATING BIO-MATERIALS ON STANDARD CMOS SUBSTRATES

2013 ◽  
Vol 22 (02) ◽  
pp. 1250081 ◽  
Author(s):  
FAISAL T. ABU-NIMEH ◽  
FATHI M. SALEM
Keyword(s):  
High Speed ◽  
High Efficiency ◽  
Low Cost ◽  
Magnetic Bead ◽  
Column Switching ◽  
Parallel Operation ◽  
Coil Array ◽  
Lab On Chip ◽  
On Chip ◽  
Array Sensing

We present a low-cost, low-power, high efficiency, and portable integrated implementations of a lab-on-chip for magnetic molecular level sensing manipulation, and diagnosis. The design features an all-integrated programmable magnetic coil array for sensing and actuating small magnetic bead objects. The coil array is selectively and dynamically controlled using the smallest permissible vertical coil inductors in this technology. Each cell, composed of the coil and its logical control circuitry, can detect small objects in the order of 1 μm diameter as well as emit eight programmable magnetic field levels for manipulation. All array sensing and driving components are shared to reduce the overall imprint. They are tuned towards the 900 s MHz ISM band and incorporating high-speed serial row/column switching up to 40 MHz for seamless pseudo-parallel operation.

scholarly journals Architecture and implementation of a high frame-rate stereo vision system

2021 ◽  
Author(s):  
Jamin Islam
Keyword(s):  
Integrated Circuits ◽  
Stereo Vision ◽  
High Speed ◽  
Vision System ◽  
Low Cost ◽  
Cost Effective ◽  
Frame Rate ◽  
Superior Performance ◽  
High Frame Rate ◽  
Stereo Vision System

For the purpose of autonomous satellite grasping, a high-speed, low-cost stereo vision system is required with high accuracy. This type of system must be able to detect an object and estimate its range. Hardware solutions are often chosen over software solutions, which tend to be too slow for high frame-rate applications. Designs utilizing field programmable gate arrays (FPGAs) provide flexibility and are cost effective versus solutions that provide similar performance (i.e., Application Specific Integrated Circuits). This thesis presents the architecture and implementation of a high frame-rate stereo vision system based on an FPGA platform. The system acquires stereo images, performs stereo rectification and generates disparity estimates at frame-rates close to 100 fpSi and on a large-enough FPGA, it can process 200 fps. The implementation presents novelties in performance and in the choice of the algorithm implemented. It achieves superior performance to existing systems that estimate scene depth. Furthermore, it demonstrates equivalent accuracy to software implementations of the dynamic programming maximum likelihood stereo correspondence algorithm.

scholarly journals Passivity Preserving Model Order Reduction Using the Reduce Norm Method

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 964
Author(s):  
Namra Akram ◽  
Mehboob Alam ◽  
Rashida Hussain ◽  
Asghar Ali ◽  
Shah Muhammad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Model Order Reduction ◽  
High Speed ◽  
Order Reduction ◽  
Reliable Operation ◽  
Model Order ◽  
Reduced Order ◽  
Reduction Methods ◽  
On Chip

Modeling and design of on-chip interconnect, the interconnection between the components is becoming the fundamental roadblock in achieving high-speed integrated circuits. The scaling of interconnect in nanometer regime had shifted the paradime from device-dominated to interconnect-dominated design methodology. Driven by the expanding complexity of on-chip interconnects, a passivity preserving model order reduction (MOR) is essential for designing and estimating the performance for reliable operation of the integrated circuit. In this work, we developed a new frequency selective reduce norm spectral zero (RNSZ) projection method, which dynamically selects interpolation points using spectral zeros of the system. The proposed reduce-norm scheme can guarantee stability and passivity, while creating the reduced models, which are fairly accurate across selected narrow range of frequencies. The reduced order results indicate preservation of passivity and greater accuracy than the other model order reduction methods.

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