A low latency and high efficient three-dimension Network-on-Chip based on hierarchical structure

Currently, the majority of the Network-on-Chip (NoC) researches are based on 2D algorithm or simple 3D structure. However, the congestion and faulty links in the topology can increase the latency and power consumption. In this paper, the authors try to build a novel 3D topology based on hierarchical structure and TSV links which can reduce the latency and power consumption by decreasing the hops during the process of passing the packets. We employ the C++ tool to test our method, and the results show that the performance can be improved about 21%–36% in throughput, also 3%–11% in latency.

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Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

JOURNAL OF ELECTRONICS INFORMATION TECHNOLOGY ◽

10.3724/sp.j.1146.2012.00654 ◽

2014 ◽

Vol 35 (2) ◽

pp. 341-346

Author(s):

Xiao-fu Zheng ◽

Hua-xi Gu ◽

Yin-tang Yang ◽

Zhong-fan Huang

Keyword(s):

Network On Chip ◽

Low Latency ◽

Router Architecture ◽

On Chip

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Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches

Electronics ◽

10.3390/electronics9020346 ◽

2020 ◽

Vol 9 (2) ◽

pp. 346 ◽

Cited By ~ 1

Author(s):

Lili Shen ◽

Ning Wu ◽

Gaizhen Yan

Keyword(s):

Power Consumption ◽

Thermal Management ◽

System Performance ◽

Control Policy ◽

Three Dimension ◽

Processor Core ◽

Management Scheme ◽

And Performance ◽

On Chip ◽

Silicon Vias

By using through-silicon-vias (TSV), three dimension integration technology can stack large memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory access and enhance system performance. However, the integration of more on-chip caches increases chip power density, which might lead to temperature-related issues in power consumption, reliability, cooling cost, and performance. An effective thermal management scheme is required to ensure the performance and reliability of the system. In this study, a fuzzy-based thermal management scheme (FBTM) is proposed that simultaneously considers cores and stacked caches. The proposed method combines a dynamic cache reconfiguration scheme with a fuzzy-based control policy in a temperature-aware manner. The dynamic cache reconfiguration scheme determines the size of the cache for the processor core according to the application that reaches a substantial amount of power consumption savings. The fuzzy-based control policy is used to change the frequency level of the processor core based on dynamic cache reconfiguration, a process which can further improve the system performance. Experiments show that, compared with other thermal management schemes, the proposed FBTM can achieve, on average, 3 degrees of reduction in temperature and a 41% reduction of leakage energy.

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Low Latency and Energy Efficient Optical Network-on-Chip Using Wavelength Assignment

IEEE Photonics Technology Letters ◽

10.1109/lpt.2012.2226939 ◽

2012 ◽

Vol 24 (24) ◽

pp. 2296-2299 ◽

Cited By ~ 15

Author(s):

Zheng Chen ◽

Huaxi Gu ◽

Yintang Yang ◽

Ke Chen

Keyword(s):

Energy Efficient ◽

Optical Network ◽

Network On Chip ◽

Wavelength Assignment ◽

Low Latency ◽

On Chip

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Design of Router Supporting Multiply Routing Algorithm for NoC

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.981.431 ◽

2014 ◽

Vol 981 ◽

pp. 431-434

Author(s):

Zhan Peng Jiang ◽

Rui Xu ◽

Chang Chun Dong ◽

Lin Hai Cui

Keyword(s):

Complex System ◽

High Performance ◽

Routing Algorithm ◽

Network On Chip ◽

System On Chip ◽

Low Latency ◽

Deterministic Routing ◽

Key Features ◽

Design Challenge ◽

On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

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A bypass-based low latency network-on-chip router

IEICE Electronics Express ◽

10.1587/elex.16.20181147 ◽

2019 ◽

Vol 16 (4) ◽

pp. 20181147-20181147 ◽

Cited By ~ 2

Author(s):

Peng Guo ◽

Qingbin Liu ◽

Ruizhi Chen ◽

Lei Yang ◽

Donglin Wang

Keyword(s):

Network On Chip ◽

Low Latency ◽

On Chip

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Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

International Journal of Reconfigurable Computing ◽

10.1155/2015/570836 ◽

2015 ◽

Vol 2015 ◽

pp. 1-13 ◽

Cited By ~ 14

Author(s):

Alireza Monemi ◽

Chia Yee Ooi ◽

Muhammad Nadzir Marsono

Keyword(s):

High Performance ◽

Clock Cycle ◽

Network On Chip ◽

Operating Frequency ◽

Low Latency ◽

Core System ◽

Low Area ◽

Area Overhead ◽

Logic Cells ◽

On Chip

Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.

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