POWER-CONSTRAINED SYSTEM-ON-A-CHIP TEST SCHEDULING USING A GENETIC ALGORITHM

This paper presents an efficient approach for the test scheduling problem of core-based systems based on a genetic algorithm. The method minimizes the overall test application time of a system-on-a-chip through efficient and compact test schedules. The problem is solved using a "sessionless" scheme that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints. We present experimental results for various SOC examples that demonstrate the effectiveness of our method. The method achieved optimal test schedules in all attempted cases in a short CPU time.