RELIEF TEXTURE MAPPING ON FIELD PROGRAMMABLE GATE ARRAY

Relief texture mapping is an image-based rendering technique which can successfully support the representation of 3D surface details and view motion parallax. It has the potential to significantly increase visual realism of rendered geometry while keeping system load constant. In this paper, FPGA (Field Programmable Gate Array) chip technology is applied to this three-dimensional image warping method. A relief texture mapping system has been implemented on a reprogrammable and reconfigurable FPGA board. The algorithm is optimized for the specific architecture and the framework is customized for circuit resources, which can be flexibly changed for other structures. In our design, we take advantage of inherent parallelism of the algorithm by concatenating multiple warping engines and well organizing data in memory space. Experimental results show high image quality with improved rendering speed.

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Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA)

ASME 2019 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems ◽

10.1115/ipack2019-6514 ◽

2019 ◽

Author(s):

Robert Carroll ◽

Carlos Gutierrez ◽

Leila Choobineh ◽

Robert Geer

Keyword(s):

Field Programmable Gate Array ◽

Thermal Modeling ◽

Three Dimensional ◽

Vertical Direction ◽

Temperature Fields ◽

Junction Temperature ◽

3D Integration ◽

Equivalent Thermal Conductivity ◽

Field Programmable ◽

Gate Array

Abstract Field Programmable Gate Arrays (FPGA) are integrated circuits (ICs) which can implement virtually any digital function and can be configured by a designer after manufacturing. This is beneficial when dedicated application-specific runs are not time or cost-effective; however, this flexibility comes at the cost of a substantially higher interconnect overhead. Three-dimensional (3D) integration can offer significant improvements in the FPGA architecture by stacking multiple device layers and interconnecting them in the third or vertical dimension, through a substrate, where path lengths are greatly reduced. This will allow for a higher density of devices and improvements in power consumption, signal integrity, and delay. Further, it facilities heterogeneous integration where additional functionalities can be incorporated into the same package as the FPGA, such as sensors, memories, and RF/analog or photonic chips, etc. Traditionally, devices have always been laid out in a planar format. 3D integration is an architecture wherein multiple layers of planar devices are stacked and interconnected using through silicon vias (TSVs) in the vertical direction. This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field programmable gate array (3D-AFPGA) design based on an extension of preexisting 2D-FPGA tile designs. Since thermal management of 3D-AFPGA is important, numerical simulations performed to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and three-dimensional temperature fields in the 3D-AFPGA are developed and discussed.

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Low-Power CMOS/Nanomaterial Three-Dimensional Field Programmable Gate Array Architecture

Quantum Matter ◽

10.1166/qm.2016.1351 ◽

2016 ◽

Vol 5 (4) ◽

pp. 612-615

Author(s):

Hojjat Sharifi ◽

Fazel Sharifi ◽

Armin Belghadr

Keyword(s):

Low Power ◽

Field Programmable Gate Array ◽

Three Dimensional ◽

Array Architecture ◽

Field Programmable ◽

Low Power Cmos ◽

Gate Array

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An OpenGL Compliant Hardware Implementation of a Graphic Processing Unit Using Field Programmable Gate Array–System on Chip Technology

ACM Transactions on Reconfigurable Technology and Systems ◽

10.1145/3410357 ◽

2021 ◽

Vol 14 (1) ◽

pp. 1-24

Author(s):

Alexander E. Beasley ◽

C. T. Clarke ◽

R. J. Watson

Keyword(s):

Field Programmable Gate Array ◽

Hardware Implementation ◽

Graphic Processing Unit ◽

System On Chip ◽

Processing Unit ◽

Chip Technology ◽

Field Programmable ◽

Gate Array ◽

On Chip ◽

Graphic Processing

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Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA) With Through Silicon Via and Copper Pillar Bonding Approach

Journal of Electronic Packaging ◽

10.1115/1.4046848 ◽

2020 ◽

Vol 142 (3) ◽

Author(s):

Leila Choobineh ◽

Robert Carrol ◽

Carlos Gutierrez ◽

Robert Geer

Keyword(s):

Temperature Distribution ◽

Field Programmable Gate Array ◽

Thermal Modeling ◽

Three Dimensional ◽

Test Structure ◽

Integration Process ◽

3D Integration ◽

Field Programmable ◽

Gate Array ◽

Bond Pads

Abstract This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field-programmable gate array (3D-AFPGA) design based on an extension of pre-existing two-dimensional-field-programmable gate array (2D-FPGA) tile designs. The periodic nature of FPGAs permits the use of an alternative approach, whereby the design entails splitting the FPGA design along tile borders and inserting through silicon vias (TSVs) at regular spatial intervals. This serves to enable true 3D performance (i.e., full 3D signal routing) while leaving most of the 2D circuit layouts intact. 3D signal buffers are inserted to handle communication between vertical and adjacent neighbors. For this approach, the density of vertical interconnections was shown to be determined by the size of the bond pads used for tier–tier communications and bonding. As a consequence, reducing bond pad dimensions from 25 μm to 15 μm, or 10 μm, bond pads are preferred to increase the connectivity between layers. A 3D-AFPGA mockup test structure was then proposed for completing development and exercising the 3D integration process flows. This mockup test structure consists of a three-tier demonstration vehicle consisting of a chip-to-wafer and a subsequent chip-to-chip bond. Besides, an alternate copper bonding approach using pillars was explored. Although the intended application is for the 3D integration process compatible with the 3D AFPGA design, the test structure was also designed to be generally applicable to various applications for 3D integration. Because of the importance of thermal management of 3D-AFPGA, it is important to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and the 3D temperature distribution in the 3D-AFPGA are developed and discussed as well.

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