Novel low quantum cost reversible logic based full adders for DSP applications

2021 ◽  
Author(s):  
M. C. Parameshwara ◽  
M. Nagabushanam
Keyword(s):  
Reversible Logic ◽  
Quantum Cost ◽  
Dsp Applications

scholarly journals Fault Tolerance in Reversible Logic Circuits and Quantum Cost Optimization

2020 ◽  
Vol 39 (5) ◽  
pp. 1099-1116
Author(s):  
Kamaraj Arunachalam ◽  
Marichamy Perumalsamy ◽  
Kaviyashri K. Ponnusamy
Keyword(s):  
Fault Tolerance ◽  
Cost Optimization ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost

A Novel ALU Circuit based on Reversible Logic

2019 ◽  
Vol 29 (11) ◽  
pp. 2050172
Author(s):  
Arindam Banerjee ◽  
Debesh Kumar Das
Keyword(s):  
Cost Reduction ◽  
Delay Line ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Logic Function ◽  
Fabrication Cost

We propose a new ALU circuit based on reversible logic. The ALU circuit implements two addition methodologies. The outputs are generated at some fixed lines for each arithmetic or logic function. A satisfactory tradeoff is achieved between the line count and the quantum cost. Reduction in ancillary inputs and garbage outputs causes a decrease in fabrication cost. The proposed designs outperform the earlier designs with respect to delay, line count and number of operations. The libraries NOT–CNOT–V–[Formula: see text] are used to optimize the quantum cost of the proposed designs.

Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter

2018 ◽  
Vol 27 (12) ◽  
pp. 1850184 ◽  
Author(s):  
Heranmoy Maity ◽  
Arijit Kumar Barik ◽  
Arindam Biswas ◽  
Anup Kumar Bhattacharjee ◽  
Anita Pal
Keyword(s):  
Logic Gate ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Combinational Logic ◽  
Quantum Cost ◽  
Code Converter ◽  
Garbage Output ◽  
Combinational Logic Circuits ◽  
Logic Functions

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.

Design of Combinational Circuits Using Reversible Decoder in Tanner Tools

2020 ◽  
Vol 17 (4) ◽  
pp. 1743-1751
Author(s):  
R. Kannan ◽  
K. Vidhya
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Logic Gates ◽  
Full Adder ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Combinational Circuits ◽  
Nano Technology ◽  
Feynman Gate ◽  
Reversible Logic Gates

Reversible logic is the emerging field for research in present era. The aim of this paper is to realize different types of combinational circuits like full-adder, full-subtractor, multiplexer and comparator using reversible decoder circuit with minimum quantum cost. Reversible decoder is designed using Fredkin gates with minimum Quantum cost. There are many reversible logic gates like Fredkin Gate, Feynman Gate, Double Feynman Gate, Peres Gate, Seynman Gate and many more. Reversible logic is defined as the logic in which the number output lines are equal to the number of input lines i.e., the n-input and k-output Boolean function F(X1,X2,X3, ...,Xn) (referred to as (n,k) function) is said to be reversible if and only if (i) n is equal to k and (ii) each input pattern is mapped uniquely to output pattern. The gate must run forward and backward that is the inputs can also be retrieved from outputs. When the device obeys these two conditions then the second law of thermo-dynamics guarantees that it dissipates no heat. Fan-out and Feed-back are not allowed in Logical Reversibility. Reversible Logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc. Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption. The comparative study in terms of garbage outputs, Quantum Cost, numbers of gates are also presented. The Circuit has been implemented and simulated using Tannaer tools v15.0 software.

scholarly journals Reversible Gate Logic Adder with Parity Preserving Design

2021 ◽  
Vol 1 (2) ◽  
Author(s):  
Kannadasan K
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Error Detection ◽  
High Speed ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Main Challenge ◽  
Wide Range

Reversible logic circuits have drawn attention from a variety of fields, including nanotechnology, optical computing, quantum computing, and low-power CMOS design. Low-power and high-speed adder cells (like the BCD adder) are used in binary operation-based electronics. The most fundamental digital circuit activity is binary addition. It serves as a foundation for all subsequent mathematical operations. The main challenge today is to reduce the power consumption of adder circuits while maintaining excellent performance over a wide range of circuit layouts. Error detection in digital systems is aided by parity preservation. This article proposes a concept for a fault-tolerant parity- preserving BCD adder. To reduce power consumption and circuit quantum cost, the proposed method makes use of reversible logic gates like IG, FRG, and F2G. Comparing the proposed circuit to the current counterpart, it has fewer constant inputs and garbage outputting devices and is faster.

scholarly journals A shared-cube approach to ESOP-based synthesis of reversible logic

2011 ◽  
Vol 24 (3) ◽  
pp. 385-402 ◽  
Author(s):  
Noor Nayeem ◽  
Jacqueline Rice
Keyword(s):  
Power Loss ◽  
Heat Dissipation ◽  
Logic Synthesis ◽  
Reversible Logic ◽  
Experimental Results ◽  
Quantum Cost ◽  
Toffoli Gate ◽  
Gate Count ◽  
Computing Industry ◽  
Synthesis Approach

Reversible logic is being suggested as a possibility for overcoming potential power loss and heat dissipation problems that the computing industry may soon be at a loss to overcome. However, for reversible logic to be a solution we must have techniques for synthesizing function descriptions to reversible circuits. This paper presents an improved ESOP-based reversible logic synthesis approach which leverages situations where cubes are shared by multiple outputs and ensures that the implementation of each cube requires just one Toffoli gate. It has the potential to minimize both gate count and quantum cost, and in fact our experimental results show that this technique can reduce the quantum cost up to 75% compared to results from the existing work.

Estimation of Power for Reversible Subtractors

2018 ◽  
Vol 7 (4.5) ◽  
pp. 102
Author(s):  
E. V.Naga Lakshmi ◽  
Dr. N.Siva Sankara Reddy
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Garbage Output ◽  
Reversible Logic Gates

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG).   Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor.  Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.  

A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate

2015 ◽  
Vol 11 (1) ◽  
pp. 36-49
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Power Loss ◽  
Optical Computing ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Processing Unit ◽  
Quantum Cost ◽  
Central Processing ◽  
Control Circuits

In the recent scenario of microelectronic industry, the reversible logic is considered as the burgeonic technology for digital circuit designing. It deals with the aim to generate digital circuits with zero power loss characteristics. Optical computing, Nanotechnology, Low power CMOS design and Digital Signal Processing (DSP) processors are leading areas of development with the concept of reversible logic. Researchers have already proposed various subsystems of the computer for the creation of low power loss devices with the help of numerous available reversible logic gates. Here in this paper, the authors have proposed a new reversible gate named as CDSM gate with 4×4 size. This CDSM gate is used to design optimized 4-bit binary comparator. The optimization is improved as compared to the existing designs based on some significant performance parameters such as total number of gates, garbage outputs generated, constant inputs and quantum cost. Comparators are widely used in various computing applications such as counters, convertor, Central Processing Unit (CPU) and control circuits etc. The comparator circuits using reversible logic can be visualized as a low power loss subsystem for the development of improved digital systems.

Efficient designs of reversible BCD to EX-3 Converter with low quantum cost in nanoscale

2020 ◽  
Vol 18 (05) ◽  
pp. 2050020 ◽  
Author(s):  
Mojtaba Noorallahzadeh ◽  
Mohammad Mosleh
Keyword(s):  
Quantum Computing ◽  
Optical Computing ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Computing Systems ◽  
Gate Count ◽  
Reversible Gate ◽  
Significant Research ◽  
Research Domain ◽  
Better Than

As an interesting and significant research domain, reversible logic is massively utilized in technologies, including optical computing, cryptography, quantum computing, nanotechnology, and so on. The realization of quantum computing is not possible without the implementation of reversible logic, and reversible designs are presented mainly to minimize the thermal loss because of the data input bits lost in the irreversible circuit. Digital converters, as the most important logic circuits, are used to connect computing systems with different binary codes. This paper first proposes a new reversible gate called Reversible Noorallahzadeh[Formula: see text]Mosleh Gate (RNMG). Then, using the proposed RNMG gate as well as existing NMG1, NMG6, and PG gates, three different designs of reversible Binary-Coded Decimal (BCD) to EX-3 code converter are proposed. Our results indicate that the proposed BCD to EX-3 code converters are superior to previous designs in terms of quantum cost. Moreover, the proposed converters are comparable or better than previous designs in terms of gate count, constant inputs, and garbage outputs.

A new design of a low-power reversible Vedic multiplier

2020 ◽  
Vol 18 (03) ◽  
pp. 2050002
Author(s):  
Meysam Rashno ◽  
Majid Haghparast ◽  
Mohammad Mosleh
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Reversible Logic ◽  
Arithmetic Circuits ◽  
Quantum Cost ◽  
Computing Systems ◽  
Vedic Multiplier ◽  
Wide Range ◽  
Logic Unit

In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.

Sign in / Sign up

Export Citation Format

Share Document