Suppression of Stand-by Tunnel Current in Ultra-Thin Gate Oxide MOSFETs by Dual Oxide Thickness-Multiple Threshold Voltage CMOS (DOT-MTCMOS)

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel theory gate tunneling current predicting model using integral approach is presented in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using HSPICE simulator. The simulation results in BSIM4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.

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Analytical model for threshold voltage shift due to impurity penetration through a thin gate oxide

IEEE Transactions on Electron Devices ◽

10.1109/16.622592 ◽

1997 ◽

Vol 44 (9) ◽

pp. 1386-1392 ◽

Cited By ~ 3

Author(s):

K. Suzuki

Keyword(s):

Analytical Model ◽

Threshold Voltage ◽

Gate Oxide ◽

Threshold Voltage Shift ◽

Voltage Shift ◽

Thin Gate Oxide

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Initiated tunnel current through thin gate oxide generation of minority carriers in Si-MIS-structures

10.1117/12.562734 ◽

2004 ◽

Author(s):

G. V. Chucheva ◽

A. S. Dudnikov ◽

E. I. Goldman ◽

N. A. Zaitsev ◽

Alexander G. Zhdan

Keyword(s):

Gate Oxide ◽

Tunnel Current ◽

Thin Gate Oxide ◽

Minority Carriers ◽

Mis Structures

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Investigation of Quasi-Breakdown Mechanism in Ultrathin Gate Oxides

MRS Proceedings ◽

10.1557/proc-592-111 ◽

1999 ◽

Vol 592 ◽

Author(s):

Hao Guan ◽

Y. D. He ◽

M. F. Li ◽

Byung Jin Cho ◽

Zhong Dong

Keyword(s):

Stress Condition ◽

Impact Ionization ◽

Gate Oxide ◽

Oxide Thickness ◽

Metastable States ◽

Switching Noise ◽

Onset Point ◽

Before And After ◽

Carrier Separation ◽

Thin Gate Oxide

ABSTRACTThe conduction mechanism of quasi-breakdown (QB) for ultra-thin gate oxide has been studied in dual-gate CMOSFET with a 3.7 nm thick gate oxide. Systematic carrier separation experiments were conducted to investigate the evolutions of gate, source/drain, and substrate currents before and after gate oxide QB. Our experimental results clearly show that QB is due to the formation of a local physically-damaged-region (LPDR) at Si/SiO2 interface. At this region, the effective oxide thickness is reduced to the direct tunneling (DT) regime. The observed high gate leakage current is due to DT electron or hole currents through the region where the LPDR is generated. Under substrate injection stress condition, there is several orders of magnitude increase of Isub(Is/d) at the onset point of QB for n(p) - MOSFET, which mainly corresponds to valence electrons DT from the substrate to the gate. Consequently, cold holes are left in the substrate and measured as substrate current. Under gate injection stress condition, there is sudden drop and even change of sign of Isub(Is/d) at the onset point of QB for n(p)-MOSFET, which corresponds to the disappearance of impact ionization and the appearance of hole DT current from the substrate to the gate. In the LPDR region, the damaged structure may have two or multi metastable states corresponding to different effective oxide thickness. The thermal transition between two or multi metastable states leads to random telegraph switching noise (RTSN) fluctuation between two or multi levels.

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Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v9i1.pp163-169 ◽

2019 ◽

Vol 9 (1) ◽

pp. 163

Author(s):

Hakkee Jung

Keyword(s):

Threshold Voltage ◽

Tunneling Current ◽

Gate Oxide ◽

Oxide Thickness ◽

Channel Length ◽

Double Gate ◽

Short Channel ◽

Double Gate Mosfet ◽

Channel Effects ◽

Channel Thickness

Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.

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A Model of Threshold Voltage in FinFET

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.216.167 ◽

2011 ◽

Vol 216 ◽

pp. 167-170

Author(s):

Jian Liu ◽

Li Li ◽

X.H. Zhang

Keyword(s):

Numerical Simulation ◽

Threshold Voltage ◽

Doping Concentration ◽

Gate Oxide ◽

Oxide Thickness ◽

Polysilicon Gate ◽

Gate Oxide Thickness ◽

Threshold Voltage Model

A physics-based threshold voltage model is proposed, according to the electrostatics distribution in Si body of FinFET which is obtained by 2-D numerical simulation. Threshold voltage of FinFET calculated from the model is matched with results of numerical simulation. Influences of polysilicon gate doping concentration, Si body doping concentration, the width and height of Si body and the gate oxide thickness on threshold voltage were investigated. As results,Si body doping concentration, gate doping concentration and the width of Si body have been found to be the most important parameters for the design of threshold voltage of FinFET-like devices.

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