3D Analytical Modeling Of Surface Potential And Threshold Voltage Model Of Dm Fintfet With Dual Hetero Gate Oxide Structure

This paper proposed on basis of a perimeter-weighted-sum method for the construction of a 3D-Analytical Modeling of double metalFin structure TFET with dual hetero gate oxide structure. The DM model device dividing into a symmetrical and asymmetrical dual-gate TFETs, and then resolving 3D architectures. The surface potential and the electrical field (E) achieved by resolving the Poisson 3D equation. The drain current (ID) is eventually calculated using Kane tunneling model to calculate the tunneling generation rate. Threshold voltage model also developed based on the charge inversion model. The performance analysis of dual hetero gate oxide Fin TFET device together with dual dielectric engineering techniques results in enhanced drain current and reduced SCE’s of low leakage current, threshold voltage roll-off and drain induced barrier lowering.

Analysis of Underlap Strained Silicon on Insulator MOSFET for Accurate and Compact Modeling

Recently, transistors with an underlapped gate structure have been widely studied to overcome several challenges associated with nanoscale devices. In this work, underlap region is incorporated at source and drain (S/D) ends in a fully depleted Strained Silicon On Insulator (SSOI) device, with high-k dielectric material in the spacer region. The S/D underlapped region helps to reduce the leakage current and can be particularly useful for low power applications. However, increased underlap length degrades the ON current significantly. We show that this issue can be mitigated via the inclusion of a high-k spacer, which improves the ON current by enhancing the gate controllability over the S/D underlap channel region. It helps to achieve the essential requirement low power applications i.e. the high ON/OFF current ratio at extremely low value of leakage current. The strained silicon material is used in the channel region to further improve the ON current. A compact threshold voltage model is developed for the proposed device (underlap-SSOI) while maintaining the accuracy at par with TCAD simulations. This threshold voltage model incorporates underlap length, strain-induced offsets and spacer dielectric constant. This device model may be used for circuit simulations.

A Temperature-Dependent Threshold Voltage Model for SiGe Source/Drain Si–NT JLFET

In this paper, we investigate the impact of temperature on threshold voltage in the SiGe source/drain silicon-nanotube junctionless field effect transistor (NT JLFET). A threshold voltage model has been derived with inclusion of temperature for presented device. It is found that when the temperature increases from T = 300 K, T = 400 K, and T = 500 K, the strain produced by the SiGe source/drain on channel has been relaxed. However, the elevated temperature decreases the potential and the electric field in channel due to increases in intrinsic carrier concentration which further shifts the Fermi level towards the band gap. It has been evaluating that the threshold voltage roll-off and the short channel effects increases due to increases in temperature. The numerical results of threshold voltage model have been well compared with results of 2-D technology computer aided design (TCAD) simulations.