scholarly journals Hardware overhead analysis of programmability in ARX crypto processing

Author(s):  
Mohamed El-Hadedy ◽  
Kevin Skadron
Keyword(s):  
Author(s):  
Friedrich Schwamm

One of the main requirements for modern FADEC systems is to implement great computing power with many interfaces and to keep the FADEC hardware effort to a minimum. On the other side the criticality potential of computer failures is considered as ‘hazardous’. The trend in FADEC development is to implement even more complex functions into the control software which consequently increases the authority and therefore the criticality potential of computer failures. In the mid 80’s a double computer system was used to performed a parallel execution of the control software with identical input parameters to output identical results. A difference in any one of these computer results causes the comparator hardware to output a failure indication. This was considered to have a 100% coverage of computer failures. The problem with this system was certainly the relatively large hardware overhead and the limited intelligence of the comparator logic. Some other FADEC systems have implemented only a Watch Dog Timer and Bus Access Supervisory hardware to detect computer malfunctions. With this method the proof for the achievements of the safety requirements have become almost impossible since adequate fault models of the computer components are difficult to establish due to their increasing functional complexity. This paper describes how to develop the safety features for the Computer Design from the Engine Control System Safety Requirements to achieve a full coverage of the potentially critical failure effects with fault tolerant failure recovery functions and a minimum of hardware overhead.


2021 ◽  
Author(s):  
Kwangrae Kim ◽  
Jeonghyun Woo ◽  
Junsu Kim ◽  
Ki-Seok Chung
Keyword(s):  

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 52 ◽  
Author(s):  
Weike Wang ◽  
Xiaobing Zhang ◽  
Qiang Hao ◽  
Zhun Zhang ◽  
Bin Xu ◽  
...  

At present, the embedded systems are facing various kinds of attacks, especially for the data stored in the external memories. This paper presents a hardware-enhanced protection method to protect the data integrity and confidentiality at runtime, preventing the data from spoofing attack, splicing attack, replay attack, and some malicious analysis. For the integrity protection, the signature is calculated by the hardware implemented Lhash engine before the data sending off the chip, and the signature of the data block is recalculated and compared with the decrypted one at the load time. For the confidentiality protection, an AES encryption engine is used to generate the key stream, the plain data and the cipher data can translate through a simple XOR operation. The hardware cryptographic engines are optimized to work simultaneously with the memory access operation, which reduces the hardware overhead and the performance overhead. We implement the proposed architecture within OR1200 processor on Xilinx Virtex 5 FPGA platform. The experiment results show that the proposed hardware-enhanced protection method can preserve the integrity and confidentiality of the runtime data in the embedded systems with low power consumption and a marginal area footprint. The performance overhead is less than 2.27% according to the selected benchmarks.


VLSI Design ◽  
1994 ◽  
Vol 2 (3) ◽  
pp. 185-198
Author(s):  
Chien-In Henry Chen

An efficient, unified algorithm, Advanced Two-Phase Cluster Partitioning, is proposed for automated synthesis of pseudo-exhaustive test generator for Built-In Self-Test (BIST) design. A prototype of the algorithm, Two-Phase Cluster Partitioning, has been proposed and the hierarchical design procedure is computationally efficient and produces test generation circuitry with low hardware overhead. However, in certain worst case, the algorithm may generate a sub-optimal design which requires more test patterns and/or hardware overhead. In order to generate a globally optimal design, further improvement of two-phase algorithm can be achieved by expanding the design space for the formation of linear sum so that the number of test signals required for pseudo-exhaustive testing can be reduced. We demonstrate the effectiveness of our approach by presenting detailed comparisons of our results against those that would be obtained by existing techniques.


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