scholarly journals Partitioning Techniques for Built-In Self-Test Design

VLSI Design ◽  
1994 ◽  
Vol 2 (3) ◽  
pp. 185-198
Author(s):  
Chien-In Henry Chen
Keyword(s):  
Optimal Design ◽  
Design Procedure ◽  
Computationally Efficient ◽  
Two Phase ◽  
Worst Case ◽  
Hardware Overhead ◽  
Phase Cluster ◽  
Unified Algorithm ◽  
Self Test ◽  
Built In Self Test

An efficient, unified algorithm, Advanced Two-Phase Cluster Partitioning, is proposed for automated synthesis of pseudo-exhaustive test generator for Built-In Self-Test (BIST) design. A prototype of the algorithm, Two-Phase Cluster Partitioning, has been proposed and the hierarchical design procedure is computationally efficient and produces test generation circuitry with low hardware overhead. However, in certain worst case, the algorithm may generate a sub-optimal design which requires more test patterns and/or hardware overhead. In order to generate a globally optimal design, further improvement of two-phase algorithm can be achieved by expanding the design space for the formation of linear sum so that the number of test signals required for pseudo-exhaustive testing can be reduced. We demonstrate the effectiveness of our approach by presenting detailed comparisons of our results against those that would be obtained by existing techniques.

scholarly journals Measuring Static Parameters of Embedded ADC Core

2011 ◽  
Vol 62 (2) ◽  
pp. 80-86
Author(s):  
Franc Novak ◽  
Peter Mrak ◽  
Anton Biasizzo
Keyword(s):  
Feasibility Study ◽  
Theoretical Background ◽  
System On Chip ◽  
Test Time ◽  
Hardware Overhead ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip ◽  
The Impact ◽  
Minimal Hardware

Measuring Static Parameters of Embedded ADC CoreThe paper presents the results of a feasibility study of measuring static parameters of ADC cores embedded in a System-on-Chip. Histogram based technique is employed because it is suitable for built-in self-test. While the theoretical background of the technique has been covered by numerous papers, less attention has been given to implementations in practice. Our goal was the implementation of histogram test in a IEEE Std 1500 wrapper. Two different solutions pursuing either minimal test time or minimal hardware overhead are described. The impact of MOS switches at ADC input on the performed measurements was considered.

An Efficient Implementation of Built in Self Diagnosis for Low Power Test Pattern Generator

2015 ◽  
Vol 3 (2) ◽  
pp. 269-272
Author(s):  
N. Nithya
Keyword(s):  
Test Pattern ◽  
Test Session ◽  
Linear Feedback ◽  
Compression Scheme ◽  
Power Requirement ◽  
Extreme Response ◽  
Hardware Overhead ◽  
Self Test ◽  
Built In Self Test ◽  
Diagnostic Resolution

A New architecture of Built-In Self-Diagnosis is presented in this project. The logic Built-In-Self-Test architecture method is extreme response compaction architecture. This architecture first time enables an autonomous on-chip evaluation of test responses with negligible hardware overhead. Architecture advantage is all data, which is relevant for a subsequent diagnosis, is gathered during just one test session. Due to some reasons, the existing method Built-In Self-Test is less often applied to random logic than to embedded memories.  The generation of deterministic test patterns can become prohibitively high due to hardware overhead. The diagnostic resolution of compacted test responses is in many cases poor and the overhead required for an acceptable resolution may become too high.  Modifications in Linear Feedback Shift Register to generate test pattern with security for modified Built-In-Self-Test applications with reduced power requirement. The modified Built-In-Self-Test circuit incorporates a fault syndrome compression scheme and improves the circuit speed with reduction of time.

RF Phase Error Built-In-Self-Test for A GSM SOC

2008 ◽  
Vol 1 (4) ◽  
pp. 39-44
Author(s):  
Dallas Webster ◽  
Loi Phan ◽  
Oren Eliezer ◽  
Rick Hudgens ◽  
Donald Lie
Keyword(s):  
Phase Error ◽  
Self Test ◽  
Built In Self Test

Fault-based Built-in Self-test and Evaluation of Phase Locked Loops

2021 ◽  
Vol 26 (3) ◽  
pp. 1-18
Author(s):  
Mehmet Ince ◽  
Ender Yilmaz ◽  
Wei Fu ◽  
Joonsung Park ◽  
Krishnaswamy Nagaraj ◽  
...  
Keyword(s):  
Phase Locked Loops ◽  
Test And Evaluation ◽  
Self Test ◽  
Built In Self Test

scholarly journals A Two-Round Optimization Design Method for Aerostatic Spindles Considering the Fluid–Structure Interaction Effect

2021 ◽  
Vol 11 (7) ◽  
pp. 3017
Author(s):  
Qiang Gao ◽  
Siyu Gao ◽  
Lihua Lu ◽  
Min Zhu ◽  
Feihu Zhang
Keyword(s):  
Optimal Design ◽  
Optimization Design ◽  
Design Method ◽  
Fluid Structure Interaction ◽  
Design Procedure ◽  
Design Parameters ◽  
Geometrical Parameters ◽  
Fluid Structure ◽  
Structure Interaction ◽  
Aerostatic Spindle

The fluid–structure interaction (FSI) effect has a significant impact on the static and dynamic performance of aerostatic spindles, which should be fully considered when developing a new product. To enhance the overall performance of aerostatic spindles, a two-round optimization design method for aerostatic spindles considering the FSI effect is proposed in this article. An aerostatic spindle is optimized to elaborate the design procedure of the proposed method. In the first-round design, the geometrical parameters of the aerostatic bearing were optimized to improve its stiffness. Then, the key structural dimension of the aerostatic spindle is optimized in the second-round design to improve the natural frequency of the spindle. Finally, optimal design parameters are acquired and experimentally verified. This research guides the optimal design of aerostatic spindles considering the FSI effect.

Optimal design of 6-DOF eclipse mechanism based on task-oriented workspace

Robotica ◽  
2011 ◽  
Vol 30 (7) ◽  
pp. 1041-1048 ◽  
Author(s):  
Donghun Lee ◽  
Jongwon Kim ◽  
TaeWon Seo
Keyword(s):  
Optimal Design ◽  
Unit Length ◽  
Numerical Procedure ◽  
Design Procedure ◽  
Mass Reduction ◽  
Objective Functions ◽  
Design Efficiency ◽  
Task Oriented ◽  
Structural Mass ◽  
Optimal Set

SUMMARYWe present a new numerical optimal design for a redundant parallel manipulator, the eclipse, which has a geometrically symmetric workspace shape. We simultaneously consider the structural mass and design efficiency as objective functions to maximize the mass reduction and minimize the loss of design efficiency. The task-oriented workspace (TOW) and its partial workspace (PW) are considered in efficiently obtaining an optimal design by excluding useless orientations of the end-effector and by including just one cross-sectional area of the TOW. The proposed numerical procedure is composed of coarse and fine search steps. In the coarse search step, we find the feasible parameter regions (FPR) in which the set of parameters only satisfy the marginal constraints. In the fine search step, we consider the multiobjective function in the FPR to find the optimal set of parameters. In this step, fine search will be kept until it reaches the optimal set of parameters that minimize the proposed objective functions by continuously updating the PW in every iteration. By applying the proposed approach to an eclipse-rapid prototyping machine, the structural mass of the machine can be reduced by 8.79% while the design efficiency is increased by 6.2%. This can be physically interpreted as a mass reduction of 49 kg (the initial structural mass was 554.7 kg) and a loss of 496 mm3/mm in the workspace volume per unit length. The proposed optimal design procedure could be applied to other serial or parallel mechanism platforms that have geometrically symmetric workspace shapes.

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