Hardware-Enhanced Protection for the Runtime Data Security in Embedded Systems

At present, the embedded systems are facing various kinds of attacks, especially for the data stored in the external memories. This paper presents a hardware-enhanced protection method to protect the data integrity and confidentiality at runtime, preventing the data from spoofing attack, splicing attack, replay attack, and some malicious analysis. For the integrity protection, the signature is calculated by the hardware implemented Lhash engine before the data sending off the chip, and the signature of the data block is recalculated and compared with the decrypted one at the load time. For the confidentiality protection, an AES encryption engine is used to generate the key stream, the plain data and the cipher data can translate through a simple XOR operation. The hardware cryptographic engines are optimized to work simultaneously with the memory access operation, which reduces the hardware overhead and the performance overhead. We implement the proposed architecture within OR1200 processor on Xilinx Virtex 5 FPGA platform. The experiment results show that the proposed hardware-enhanced protection method can preserve the integrity and confidentiality of the runtime data in the embedded systems with low power consumption and a marginal area footprint. The performance overhead is less than 2.27% according to the selected benchmarks.

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Low Power Testing

Design and Test Technology for Dependable Systems-on-Chip - Advances in Computer and Electrical Engineering ◽

10.4018/978-1-60960-212-3.ch018 ◽

2011 ◽

pp. 395-412

Author(s):

Zdenek Kotásek ◽

Jaroslav Škarvada

Keyword(s):

Embedded Systems ◽

Power Consumption ◽

Low Power ◽

Low Power Consumption ◽

Operational Mode ◽

Dynamic Power ◽

Low Power Testing ◽

Test Application ◽

Basic Concepts ◽

Power Testing

Portable computer systems and embedded systems are examples of electronic devices which are powered from batteries; therefore, they are designed with the goal of low power consumption. Low power consumption becomes important not only during normal operational mode, but during test application as well when switching activity is higher than in normal mode. In this chapter, a survey of basic concepts and methodologies from the area of low power testing is provided. It is explained here how power consumption is related to switching activities during test application. The concepts of static and dynamic power consumption are discussed together with metrics which can be possibly used to evaluate power consumption. The survey of methods, the goal of which is to reduce dynamic power consumption during test application, is then provided followed by a short survey of power-constrained test scheduling methods.

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LOW POWER CONSUMPTION SECURITY PLATFORM FOR INDUSTRIAL COMMUNICATIONS USING AN MPSOC

Journal of Circuits System and Computers ◽

10.1142/s0218126613500291 ◽

2013 ◽

Vol 22 (05) ◽

pp. 1350029

Author(s):

JOSE M. GRANADO-CRIADO ◽

MIGUEL A. VEGA-RODRÍGUEZ ◽

JOSE M. CHAVES-GONZALEZ ◽

JUAN M. SANCHEZ-PEREZ ◽

JUAN A. GOMEZ-PULIDO

Keyword(s):

Embedded Systems ◽

Power Consumption ◽

Low Power ◽

Low Power Consumption ◽

The Internet ◽

Secure Protocols ◽

Industrial Communications

This work presents a novel security platform for industrial communications using a nine-MicroBlaze MPSoC. This platform has low power consumption and cost, therefore, it is very appropriate for embedded systems, where restrictions on cost and power consumption have to be fulfilled. This system uses the RSA asymmetric algorithm combined with the AES symmetric algorithm, which was developed using two encryption modes, ECB and CBC. In this way, the platform makes possible to combine different algorithms and modes in function of the necessities of speed and security required. Furthermore, due to the implementation of standard algorithms (AES and RSA) and modes (ECB and CBC), this platform can be connected to the Internet, and can even use secure protocols as SSL.

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Dynamic Frequency Scaling Regarding Memory for Energy Efficiency of Embedded Systems

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v8i3.pp1798-1804 ◽

2018 ◽

Vol 8 (3) ◽

pp. 1798

Author(s):

Junha Kim ◽

Moonju Park

Keyword(s):

Energy Efficiency ◽

Embedded Systems ◽

Power Consumption ◽

Power Management ◽

Power Efficiency ◽

Memory Access ◽

Management Policy ◽

Dynamic Scaling ◽

Frequency Scaling ◽

Frequency Selection

Memory significantly affects the power consumption of embedded systems as well as performance. CPU frequency scaling for power management could fail in optimizing the energy efficiency without considering the memory access. In this paper, we analyze the power consumption and energy efficiency of an embedded system that supports dynamic scaling of frequency for both CPU and memory access. The power consumption of the CPU and the memory is modeled to show that the memory access rate affects the energy efficiency and the CPU frequency selection. Based on the power model, a method for frequency selection is presented to optimize the power efficiency which is measured using Energy-Delay Product (EDP). The proposed method is implemented and tested on a commercial smartphone to achieve about 3.3% - 7.6% enhancement comparing with the power management policy provided by the manufacturer in terms of EDP.

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Compositional Tuning of Negative Differential Resistance in Bulk Silver Iodide Memristor

New Journal of Chemistry ◽

10.1039/d0nj05427e ◽

2020 ◽

Author(s):

SMITA GAJANAN NAIK ◽

Mohammad Hussain Kasim Rabinal

Keyword(s):

Power Consumption ◽

Negative Differential Resistance ◽

Silver Iodide ◽

Differential Resistance ◽

Fast Response ◽

Low Power Consumption ◽

Switching Effect ◽

Memory Switching ◽

Bulk Silver ◽

Emerging Memory

Electrical memory switching effect has received a great interest to develop emerging memory technology such as memristors. The high density, fast response, multi-bit storage and low power consumption are their...

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Optimal design of a high homogeneous and small-size shim coil for atomic spin gyroscope based on 0-1 linear programming

International Journal of Applied Electromagnetics and Mechanics ◽

10.3233/jae-209319 ◽

2020 ◽

Vol 64 (1-4) ◽

pp. 165-172

Author(s):

Dongge Deng ◽

Mingzhi Zhu ◽

Qiang Shu ◽

Baoxu Wang ◽

Fei Yang

Keyword(s):

Linear Programming ◽

Power Consumption ◽

Low Power ◽

Optimization Design ◽

Structural Parameters ◽

Axial Position ◽

Low Power Consumption ◽

Optimal Method ◽

Atomic Spin ◽

Shim Coil

It is necessary to develop a high homogeneous, low power consumption, high frequency and small-size shim coil for high precision and low-cost atomic spin gyroscope (ASG). To provide the shim coil, a multi-objective optimization design method is proposed. All structural parameters including the wire diameter are optimized. In addition to the homogeneity, the size of optimized coil, especially the axial position and winding number, is restricted to develop the small-size shim coil with low power consumption. The 0-1 linear programming is adopted in the optimal model to conveniently describe winding distributions. The branch and bound algorithm is used to solve this model. Theoretical optimization results show that the homogeneity of the optimized shim coil is several orders of magnitudes better than the same-size solenoid. A simulation experiment is also conducted. Experimental results show that optimization results are verified, and power consumption of the optimized coil is about half of the solenoid when providing the same uniform magnetic field. This indicates that the proposed optimal method is feasible to develop shim coil for ASG.

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An Ultra-low Power Consumption MAC Protocol Complied with IEEE 802.15.4/4e for Wireless Smart Utility Networks

IEEJ Transactions on Electronics Information and Systems ◽

10.1541/ieejeiss.136.1555 ◽

2016 ◽

Vol 136 (11) ◽

pp. 1555-1566 ◽

Cited By ~ 6

Author(s):

Jun Fujiwara ◽

Hiroshi Harada ◽

Takuya Kawata ◽

Kentaro Sakamoto ◽

Sota Tsuchiya ◽

...

Keyword(s):

Power Consumption ◽

Low Power ◽

Ieee 802.15.4 ◽

Mac Protocol ◽

Low Power Consumption ◽

Ultra Low Power

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Efficient Instruction and Data Caching for High Performance Embedded Processors

Jornada de Jóvenes Investigadores del I3A ◽

10.26754/jji-i3a.201201788 ◽

1970 ◽

pp. 9

Author(s):

A. Ferrerón Labari ◽

D. Suárez Gracia ◽

V. Viñals Yúfera

Keyword(s):

Embedded Systems ◽

Power Consumption ◽

Low Power ◽

Interconnection Networks ◽

High Performance ◽

Critical Issue ◽

Content Management ◽

Structure Design ◽

Portable Devices ◽

On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

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