A cache consolidation design of MLC STT-RAM for energy efficiency enhancement on cyber-physical systems

Owing to the energy-constraint nature of cyber-physical systems (CPS), energy efficiency has become a primary design consideration for CPS. On CPS, owing to the high leakage power issue of SRAM, the major portion of its energy consumption comes from static random-access memory (SRAM)-based processors. Recently, with the emerging and rapidly evolving nonvolatile Spin-Transfer Torque RAM (STT-RAM), STT-RAM is expected to replace SRAM within processors for enhancing the energy efficiency with its near-zero leakage power features. The advances in Magnetic Tunneling Junction (MTJ) technology also realize the multi-level cell (MLC) STT-RAM to pack more cells with the same die area for achieving the memory density. However, the write disturbance issue of MLC STT-RAM prevents STT-RAM from properly resolving the energy efficiency of CPS. Although studies have been proposed to alleviate this issue, previous strategies could induce additional management overhead due to the use of counters or lead to frequent swap operations. Such an observation motivates us to propose an effective and simple strategy to combine direct and split cache mapping designs to enhance the energy efficiency of MLC STT-RAM. A series of experiments have been conducted on an open-source emulator with encouraging results.