Research on Noise Simulation of Dynamic Comparator

2021 ◽  
Author(s):  
Yinghao Liu ◽  
Xiaoman Wang ◽  
Xiaokun Yang ◽  
Jinwang Li ◽  
Chang Liu ◽  
...  
Author(s):  
Galina Vasil’evna Troshina ◽  
Alexander Aleksandrovich Voevoda

It was suggested to use the system model working in real time for an iterative method of the parameter estimation. It gives the chance to select a suitable input signal, and also to carry out the setup of the object parameters. The object modeling for a case when the system isn't affected by the measurement noises, and also for a case when an object is under the gaussian noise was executed in the MatLab environment. The superposition of two meanders with different periods and single amplitude is used as an input signal. The model represents the three-layer structure in the MatLab environment. On the most upper layer there are units corresponding to the simulation of an input signal, directly the object, the unit of the noise simulation and the unit for the parameter estimation. The second and the third layers correspond to the simulation of the iterative method of the least squares. The diagrams of the input and the output signals in the absence of noise and in the presence of noise are shown. The results of parameter estimation of a static object are given. According to the results of modeling, the algorithm works well even in the presence of significant measurement noise. To verify the correctness of the work of an algorithm the auxiliary computations have been performed and the diagrams of the gain behavior amount which is used in the parameter estimation procedure have been constructed. The entry conditions which are necessary for the work of an iterative method of the least squares are specified. The understanding of this algorithm functioning principles is a basis for its subsequent use for the parameter estimation of the multi-channel dynamic objects.


Author(s):  
Wataru Kitagawa ◽  
Toshiya Kutsuna ◽  
Kazuki Kuwana ◽  
Yuki Kawamura ◽  
Takaharu Takeshita
Keyword(s):  

2012 ◽  
Vol 229-231 ◽  
pp. 1507-1510
Author(s):  
Xiang Ning Fan ◽  
Hao Zheng ◽  
Yu Tao Sun ◽  
Xiang Yan

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.


1978 ◽  
Vol 15 (2) ◽  
pp. 85-92
Author(s):  
W. S. Clapper ◽  
R. Mani ◽  
E. J. Stringas ◽  
G. Banerian
Keyword(s):  

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