Low-voltage dynamic comparator using positive feedback bulk effect on a floating inverter amplifier

Author(s):  
Bruno Canal ◽  
Hamilton D. Klimach ◽  
Sergio Bampi ◽  
Tiago R. Balen
2002 ◽  
Vol 15 (1) ◽  
pp. 93-101
Author(s):  
Lyes Bouzerara ◽  
Tahar Belaroussi ◽  
Boualem Amirouche

A low voltage, high dc gain and wideband load compensated cas code operational transconductance amplifier (OTA), using an active positive feedback with feed forward technique and frequency-dependent current mirrors (FDCM), is presented and analyzed. Such techniques stand as a powerful method of gain bandwidth and phase margin enhancements. In this paper, a frequency-dependent current mirror, whose input impedance increases with frequency, is used to form the feed forward path at the input of the current mirror with a feed forward capacitor. By using these techniques, the gain bandwidth product of the amplifier is improved from 115 MHz to 194 MHz, the phase margin is also improved from 85? to 95? and the gain is enhanced from 11 dB to 93 dB. This amplifier operates at 2.5 V power supply voltage drives a capacitive load of 1pF and gives a power dissipation of 7 mW. The predicted performance is verified by simulations using HSPICE tool with 0.8 fim CMOS AMS parameters.


2007 ◽  
Vol 43 (10) ◽  
pp. 569 ◽  
Author(s):  
B. Calvo ◽  
J. Ramírez-Angulo ◽  
S.R.S. Garimella

2017 ◽  
Vol 1 (1) ◽  
pp. 15-22 ◽  
Author(s):  
Hemlata Gururani ◽  
◽  
Rachna Arya ◽  

Author(s):  
Julie Roslita Rusli ◽  
Suhaidi Shafie ◽  
Roslina Mohd Sidek ◽  
Hasmayadi Abdul Majid ◽  
W. Z. Wan Hassan ◽  
...  

Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC).  This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed.  The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V.  The method used to verify the robustness of the comparator circuit across 45 PVT is presented.  The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The simulation result show that the proposed comparator circuit achieved significant reduction of power consumption and delay during worst case condition compared to dynamic comparator proposed from previous researchers.


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