Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology

C. Claeys; S. Iacovo; D. Kobayashi; A. Mercha; A. Griffoni; P. J. Roussel; F. Crupi; E. Simoen

doi:10.1149/05005.0213ecst

Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology

ECS Transactions ◽

10.1149/05005.0213ecst ◽

2013 ◽

Vol 50 (5) ◽

pp. 213-222

Author(s):

C. Claeys ◽

S. Iacovo ◽

D. Kobayashi ◽

A. Mercha ◽

A. Griffoni ◽

...

Keyword(s):

Statistical Evaluation ◽

Cmos Technology ◽

Radiation Hardness ◽

Proton Radiation ◽

Wafer Level ◽

Metal Gate ◽

High K ◽

High K Dielectric

Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology

ECS Meeting Abstracts ◽

10.1149/ma2012-02/32/2639 ◽

2012 ◽

Keyword(s):

Statistical Evaluation ◽

Cmos Technology ◽

Radiation Hardness ◽

Proton Radiation ◽

Wafer Level ◽

Metal Gate ◽

High K ◽

High K Dielectric

0.525μm>sup<2>/sup<6T-SRAM Bit Cell using 45nm Fully-Depleted SOI CMOS Technology with Metal gate, High K Dielectric and Elevated Source/Drain on 300mm wafers.

2005 IEEE International SOI Conference Proceedings ◽

10.1109/soi.2005.1563595 ◽

2006 ◽

Cited By ~ 1

Author(s):

A. Vandooren ◽

C. Hobbs ◽

M. Aminpur ◽

G. Chabanne ◽

A. Wild ◽

...

Keyword(s):

Cmos Technology ◽

Metal Gate ◽

Fully Depleted ◽

High K ◽

High K Dielectric ◽

Elevated Source ◽

Soi Cmos

Fully-depleted SOI CMOS technology using WXN metal gate and HfSixOyNZ high-k dielectric

ESSDERC 2007 - 37th European Solid State Device Research Conference ◽

10.1109/essderc.2007.4430926 ◽

2007 ◽

Author(s):

D. Aime ◽

C. Fenouillet-Beranger ◽

P. Perreau ◽

S. Denorme ◽

J. Coignus ◽

...

Keyword(s):

Cmos Technology ◽

Metal Gate ◽

Fully Depleted ◽

High K ◽

High K Dielectric ◽

Soi Cmos

Towards metal gate/high-k dielectric integration for high performance CMOS technology

10.7567/ssdm.2006.j-1-1 ◽

2006 ◽

Author(s):

E. Cartier

Keyword(s):

High Performance ◽

Cmos Technology ◽

Metal Gate ◽

High K ◽

High K Dielectric

Analysis of USJ Formation with Combined RTA/Laser Annealing Conditions for 28nm High-K/Metal Gate CMOS Technology Using Advanced TCAD for Process and Device Simulation

2012 International Silicon-Germanium Technology and Device Meeting (ISTDM) ◽

10.1109/istdm.2012.6222439 ◽

2012 ◽

Cited By ~ 1

Author(s):

E. M. Bazizi ◽

S. M. Pandey ◽

C. Wang ◽

I. Jiang ◽

S. Chu ◽

...

Keyword(s):

Laser Annealing ◽

Device Simulation ◽

Cmos Technology ◽

Metal Gate ◽

Annealing Conditions ◽

High K

Assessing the Performance of CMOS Amplifiers Using High-k Dielectric with Metal Gate on High Mobility Substrate

Communications in Computer and Information Science - Advances in Computing and Data Sciences ◽

10.1007/978-981-13-1810-8_28 ◽

2018 ◽

pp. 279-289

Author(s):

Deepa Anand ◽

M. Swathi ◽

A. Purushothaman ◽

Sundararaman Gopalan

Keyword(s):

High Mobility ◽

Metal Gate ◽

High K ◽

High K Dielectric

Electron Energy-Loss Spectrum Imaging of an HfSiO High-k Dielectric Stack with a TaN Metal Gate

Springer Proceedings in Physics - Microscopy of Semiconducting Materials 2007 ◽

10.1007/978-1-4020-8615-1_68 ◽

2008 ◽

pp. 313-316

Author(s):

M MacKenzie ◽

A J Craven ◽

D W McComb ◽

C M McGilvery ◽

S McFadzean ◽

...

Keyword(s):

Energy Loss ◽

Electron Energy ◽

Electron Energy Loss Spectrum ◽

Metal Gate ◽

High K ◽

Spectrum Imaging ◽

High K Dielectric ◽

Electron Energy Loss

Temperature operation of FDSOI devices with metal gate (TaSiN) and high-k dielectric

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003. ◽

10.1109/essderc.2003.1256941 ◽

2004 ◽

Cited By ~ 3

Author(s):

J. Pretet ◽

A. Vandooren ◽

S. Ciistoloveanu

Keyword(s):

Metal Gate ◽

High K ◽

High K Dielectric

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2009.2034082 ◽

2010 ◽

Vol 45 (1) ◽

pp. 103-110 ◽

Cited By ~ 32

Author(s):

Yih Wang ◽

Uddalak Bhattacharya ◽

Fatih Hamzaoglu ◽

Pramod Kolar ◽

Yong-Gee Ng ◽

...

Keyword(s):

Power Management ◽

Cmos Technology ◽

Metal Gate ◽

High K ◽

Sram Design

Dopant Segregated Schottky Source/Drain for Germanium p-MOSFETs with Metal Gate/High-k Dielectric Stack

ECS Meeting Abstracts ◽

10.1149/ma2009-02/31/2395 ◽

2009 ◽

Keyword(s):

Metal Gate ◽

High K ◽

High K Dielectric

Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology

Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology

0.525&#956;m&gt;sup&lt;2&gt;/sup&lt;6T-SRAM Bit Cell using 45nm Fully-Depleted SOI CMOS Technology with Metal gate, High K Dielectric and Elevated Source/Drain on 300mm wafers.

Fully-depleted SOI CMOS technology using WXN metal gate and HfSixOyNZ high-k dielectric

Towards metal gate/high-k dielectric integration for high performance CMOS technology

Analysis of USJ Formation with Combined RTA/Laser Annealing Conditions for 28nm High-K/Metal Gate CMOS Technology Using Advanced TCAD for Process and Device Simulation

Assessing the Performance of CMOS Amplifiers Using High-k Dielectric with Metal Gate on High Mobility Substrate

Electron Energy-Loss Spectrum Imaging of an HfSiO High-k Dielectric Stack with a TaN Metal Gate

Temperature operation of FDSOI devices with metal gate (TaSiN) and high-k dielectric

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

Dopant Segregated Schottky Source/Drain for Germanium p-MOSFETs with Metal Gate/High-k Dielectric Stack

0.525μm>sup<2>/sup<6T-SRAM Bit Cell using 45nm Fully-Depleted SOI CMOS Technology with Metal gate, High K Dielectric and Elevated Source/Drain on 300mm wafers.