0.525&#956;m&gt;sup&lt;2&gt;/sup&lt;6T-SRAM Bit Cell using 45nm Fully-Depleted SOI CMOS Technology with Metal gate, High K Dielectric and Elevated Source/Drain on 300mm wafers.

AbstractA MOSFET formed by a Si cantilever channel suspended between source/drain “anchors” wrapped all-around by high-κ dielectric and metal gate is demonstrated. The device shows excellent subthreshold characteristics and low leakage currents due to the fully depleted body and the gate-all-around architecture implemented with a high-κ dielectric and metal gate. At the same time this also allows a high drive current due to mobility enhancements arising from volume inversion of the cantilever channel such that a large ION/IOFF is achieved.

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Ultra-thin body fully-depleted SOI devices with metal gate (TaSiN) gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions

IEEE International SOI Conference SOI-02 ◽

10.1109/soi.2002.1044477 ◽

2002 ◽

Cited By ~ 8

Author(s):

Vandooren ◽

Egley ◽

Zavala ◽

Franke ◽

Barr ◽

...

Keyword(s):

Thin Body ◽

Metal Gate ◽

Fully Depleted ◽

High K ◽

Soi Devices ◽

Elevated Source

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Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology

ECS Meeting Abstracts ◽

10.1149/ma2012-02/32/2639 ◽

2012 ◽

Keyword(s):

Statistical Evaluation ◽

Cmos Technology ◽

Radiation Hardness ◽

Proton Radiation ◽

Wafer Level ◽

Metal Gate ◽

High K ◽

High K Dielectric

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Towards metal gate/high-k dielectric integration for high performance CMOS technology

10.7567/ssdm.2006.j-1-1 ◽

2006 ◽

Author(s):

E. Cartier

Keyword(s):

High Performance ◽

Cmos Technology ◽

Metal Gate ◽

High K ◽

High K Dielectric

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Mixed-signal performance of sub-100nm fully-depleted SOI devices with metal gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions

IEEE International Electron Devices Meeting 2003 ◽

10.1109/iedm.2003.1269441 ◽

2004 ◽

Cited By ~ 2

Author(s):

A. Vandooren ◽

A.V.Y. Thean ◽

Y. Du ◽

I. To ◽

J. Hughes ◽

...

Keyword(s):

Metal Gate ◽

Mixed Signal ◽

Fully Depleted ◽

High K ◽

Soi Devices ◽

Elevated Source

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Analysis of USJ Formation with Combined RTA/Laser Annealing Conditions for 28nm High-K/Metal Gate CMOS Technology Using Advanced TCAD for Process and Device Simulation

2012 International Silicon-Germanium Technology and Device Meeting (ISTDM) ◽

10.1109/istdm.2012.6222439 ◽

2012 ◽

Cited By ~ 1

Author(s):

E. M. Bazizi ◽

S. M. Pandey ◽

C. Wang ◽

I. Jiang ◽

S. Chu ◽

...

Keyword(s):

Laser Annealing ◽

Device Simulation ◽

Cmos Technology ◽

Metal Gate ◽

Annealing Conditions ◽

High K

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Assessing the Performance of CMOS Amplifiers Using High-k Dielectric with Metal Gate on High Mobility Substrate

Communications in Computer and Information Science - Advances in Computing and Data Sciences ◽

10.1007/978-981-13-1810-8_28 ◽

2018 ◽

pp. 279-289

Author(s):

Deepa Anand ◽

M. Swathi ◽

A. Purushothaman ◽

Sundararaman Gopalan

Keyword(s):

High Mobility ◽

Metal Gate ◽

High K ◽

High K Dielectric

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A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078720001087 ◽

2020 ◽

pp. 1-18

Author(s):

Florent Torres ◽

Eric Kerhervé ◽

Andreia Cathelin ◽

Magali De Matos

Keyword(s):

Power Amplifier ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Fully Depleted ◽

Technology Roadmap ◽

Wide Range ◽

28 Nm ◽

Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

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0.525μm>sup<2>/sup<6T-SRAM Bit Cell using 45nm Fully-Depleted SOI CMOS Technology with Metal gate, High K Dielectric and Elevated Source/Drain on 300mm wafers.

Fully-depleted SOI CMOS technology using WXN metal gate and HfSixOyNZ high-k dielectric

Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology

Gate-All-Around (GAA) Fully Depleted (FD) Cantilever Channel MOSFET with High-k Dielectric and Metal Gate

Ultra-thin body fully-depleted SOI devices with metal gate (TaSiN) gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions

Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology

Towards metal gate/high-k dielectric integration for high performance CMOS technology

Mixed-signal performance of sub-100nm fully-depleted SOI devices with metal gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions

Analysis of USJ Formation with Combined RTA/Laser Annealing Conditions for 28nm High-K/Metal Gate CMOS Technology Using Advanced TCAD for Process and Device Simulation

Assessing the Performance of CMOS Amplifiers Using High-k Dielectric with Metal Gate on High Mobility Substrate

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

Export Citation Format

0.525&#956;m&gt;sup&lt;2&gt;/sup&lt;6T-SRAM Bit Cell using 45nm Fully-Depleted SOI CMOS Technology with Metal gate, High K Dielectric and Elevated Source/Drain on 300mm wafers.

Fully-depleted SOI CMOS technology using WXN metal gate and HfSixOyNZ high-k dielectric

Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology

Gate-All-Around (GAA) Fully Depleted (FD) Cantilever Channel MOSFET with High-k Dielectric and Metal Gate

Ultra-thin body fully-depleted SOI devices with metal gate (TaSiN) gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions

Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology

Towards metal gate/high-k dielectric integration for high performance CMOS technology

Mixed-signal performance of sub-100nm fully-depleted SOI devices with metal gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions

Analysis of USJ Formation with Combined RTA/Laser Annealing Conditions for 28nm High-K/Metal Gate CMOS Technology Using Advanced TCAD for Process and Device Simulation

Assessing the Performance of CMOS Amplifiers Using High-k Dielectric with Metal Gate on High Mobility Substrate

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

0.525μm>sup<2>/sup<6T-SRAM Bit Cell using 45nm Fully-Depleted SOI CMOS Technology with Metal gate, High K Dielectric and Elevated Source/Drain on 300mm wafers.