The Effect of Nitrogen in a p +  Polysilicon Gate on Boron Penetration Through the Gate Oxide

1997 ◽  
Vol 144 (12) ◽  
pp. 4326-4330 ◽  
Author(s):  
Satoshi Nakayama ◽  
Tetsushi Sakai
1994 ◽  
Vol 15 (3) ◽  
pp. 109-111 ◽  
Author(s):  
Z.J. Ma ◽  
J.C. Chen ◽  
Z.H. Liu ◽  
J.T. Krick ◽  
Y.C. Cheng ◽  
...  

1993 ◽  
Vol 303 ◽  
Author(s):  
Bojun Zhang ◽  
Dennis M. Maher ◽  
Mark S. Denker ◽  
Mark A. Ray

ABSTRACTWe report a systematic study of dopant diffusion behavior for thin gate oxides and polysilicon implanted gate structures. Boron behavior is emphasized and its behavior is compared to that of As+ and BF2+. Dopant activation is achieved by rapid thermal annealing. Test structures with 100 Å, 60 Å and 30 Å gate oxides and ion implanted polysilicon gate electrodes were fabricated and characterized after annealing by SIMS, SEM, TEM, and C-V rpeasurements. For arsenic implanted structures, no dopant diffusion through a gate oxide of 30 Å thickness and an annealing condition as high as 1 100*C/1Os was observed. For boron implanted structures, as indicated by SIMS depth profiling, structures annealed at 1000*C/10s exhibit a so-called critical condition for boron diffusion through a 30 Å gate oxide. Boron dopant penetration is clearly observed for 60 Å gate oxides at an annealing condition of 1050 0C/10s. The flatband voltage shift can be as high as 0.56 volts as indicated by C-V measurements for boron penetrated gate oxides. However, 100 Å gate oxides are good diffusion barriers for boron at an annealing condition of 1100°C/10s. For BF2 implanted structures, the diffusion behavior is consistent with behavior reported in the literature.


1993 ◽  
Vol 14 (6) ◽  
pp. 304-306 ◽  
Author(s):  
Y. Taur ◽  
S. Cohen ◽  
S. Wind ◽  
T. Lii ◽  
C. Hsu ◽  
...  
Keyword(s):  

2003 ◽  
Vol 39 (10) ◽  
pp. 807 ◽  
Author(s):  
K.K. Bourdelle ◽  
A. Agarwal ◽  
A.S. Perel

1995 ◽  
Vol 387 ◽  
Author(s):  
I. Sagnes ◽  
D Laviale ◽  
F. Glowacki ◽  
B. Blanchard ◽  
F. Martin

abstractFor both advanced MOS technologies (gate length ≤ 0.25.μm) and EEPROMs, the quality and reproducibility of thin dielectric films (≤ 6 nm) are essential. To obtain such dielectrics involves very precise control of the silicon surface preparation and gate oxide growth. Furthermore, research into such supplementary properties of oxide as improved SiO2/Si interface resistance to current injections or enhanced p+gate resistance to boron penetration in the channel may require nitridation treatment. Such a sequence of steps can be carried out under controled atmosphere using a cluster tool. This paper presents the preliminary results obtained in a single wafer cluster tool on i) the surface preparation under ozone of a silicon wafer immediately after diluted liquid HF treatment and ii) the nitridation of the 6 nm gate oxide under low temperature, low pressure gaseous NO. It is shown that the NO molecule can be successfully used in Rapid Thermal Processing (RTP) and allows gate oxides to be nitrided with properties at least equivalent to those obtained under N2O nitridation, but with a strikingly reduced thermal budget.


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