Controlled Thin Oxidation and Nitridation in a Single Wafer Cluster Tool

1995 ◽  
Vol 387 ◽  
Author(s):  
I. Sagnes ◽  
D Laviale ◽  
F. Glowacki ◽  
B. Blanchard ◽  
F. Martin
Keyword(s):  
Surface Preparation ◽  
Gate Oxide ◽  
Dielectric Films ◽  
Gate Oxides ◽  
Thermal Budget ◽  
Precise Control ◽  
Boron Penetration ◽  
Gate Resistance ◽  
Thin Dielectric Films ◽  
Cluster Tool

abstractFor both advanced MOS technologies (gate length ≤ 0.25.μm) and EEPROMs, the quality and reproducibility of thin dielectric films (≤ 6 nm) are essential. To obtain such dielectrics involves very precise control of the silicon surface preparation and gate oxide growth. Furthermore, research into such supplementary properties of oxide as improved SiO2/Si interface resistance to current injections or enhanced p+gate resistance to boron penetration in the channel may require nitridation treatment. Such a sequence of steps can be carried out under controled atmosphere using a cluster tool. This paper presents the preliminary results obtained in a single wafer cluster tool on i) the surface preparation under ozone of a silicon wafer immediately after diluted liquid HF treatment and ii) the nitridation of the 6 nm gate oxide under low temperature, low pressure gaseous NO. It is shown that the NO molecule can be successfully used in Rapid Thermal Processing (RTP) and allows gate oxides to be nitrided with properties at least equivalent to those obtained under N2O nitridation, but with a strikingly reduced thermal budget.

Study of Nitrogen Incorporation in Gate Oxides Using the Resistance to Oxidation Method

1996 ◽  
Vol 429 ◽  
Author(s):  
I. Sagnes ◽  
D. Laviale ◽  
M. Regache ◽  
F. Glowacki ◽  
L. Deutschmann ◽  
...  
Keyword(s):  
Nitrogen Concentration ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Gate Oxides ◽  
Thermal Budget ◽  
Nitrogen Incorporation ◽  
Resistance To Oxidation ◽  
Low Thermal Budget ◽  
Direct Use ◽  
Low Nitrogen

Numerous nitridation processes have been studied to obtain very thin (≤ 6 nm), reproducible and reliable gate oxides. Recent results (1,2,3) have confirmed that i) the NO molecule is the species responsible for the nitrogen incorporation at the SiO2/Si interface and that ii) the direct use of NO gas allows the gate oxide to be nitrided at low thermal budget whilst maintaining the same advantages as those of N2O nitridation. NO nitridation of very thin oxides has so far been inadequately documented in terms of incorporated nitrogen concentration at the SiO2/Si interface. It is of prime importance to control the incorporation of a few nitrogen monolayers at the SiO2/Si interface, particularly for device performances in the 0. 18μm CMOS technology. In the following we present results on the control of low nitrogen concentration in pure NO atmosphere, with particular emphasis on a method based on the re-oxidation of nitrided oxides. This method can be used in a production line thus avoiding the high costs and long characterization times associated with SIMS measurements.

Comparison of Gate Oxide Processing Techniques for Thin Dielectric Films

1996 ◽  
Vol 446 ◽  
Author(s):  
Pat Schay ◽  
Fuyu Lin ◽  
Sergio Ajuria ◽  
John Stih
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Gate Dielectrics ◽  
Gate Oxide ◽  
Electrical Performance ◽  
Dielectric Films ◽  
Total Thickness ◽  
Large Area ◽  
Processing Techniques ◽  
Thin Dielectric Films

AbstractThis paper focuses on establishing a baseline for thin dielectric processes including: low temperature, dilute, stacked (TEOS), oxynitride, and high temperature annealed (grow‐anneal‐grow) oxidation. 105Å (total thickness) gate dielectrics were grown or deposited for this study. The stack oxide showed the highest Vbd yields for both large‐area and edge‐intensive capacitors, but the poorest Qbd. The N2O oxide yielded mediocre Vbd and Qbd. The low temperature and dilute oxides showed early breakdowns, but acceptable Qbd. 900°C thermal gate oxide showed slightly better average Vbd than low temperature and dilute oxides but comparable Qbd. The high temperature annealed oxide appears to have the best electrical performance, but the worst uniformity.

Ellipsometry Measurement Accuracy of Gate Oxides under Polysilicon

2003 ◽  
Vol 782 ◽  
Author(s):  
Gary Jiang ◽  
Don Pelcher ◽  
Daewon Kwon ◽  
Jana Clerico ◽  
George Collins
Keyword(s):  
Gate Dielectric ◽  
Optical Feedback ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Visible Spectral Range ◽  
Dielectric Films ◽  
High Yield ◽  
Gate Oxides ◽  
Airborne Contamination ◽  
Accuracy And Repeatability

ABSTRACTPrecisely controlling the thickness of ultrathin silicon dioxide (SiO2) gate dielectric films is critical for high yield advanced generation semiconductor manufacturing. Advanced methods for producing ultrathin gates deposit both the gate dielectric and the polysilicon (poly-Si) gate electrode in a single cluster tool. This avoids the opportunity for adsorption of molecular airborne contamination (MAC) between deposition of the two layers, but necessitates measuring gate oxide thickness through a thick poly-Si layer.Variations in poly-Si grain size, amorphous silicon content, and roughness, make it very difficult to model the optical feedback in the visible spectral range to resolve ultrathin (10–20 Å) gate oxides with sufficient accuracy and repeatability for process control.This paper studies the optical behavior of the poly-Si/dielectric filmstack from 190 nm to 900 nm and the physical properties of the poly-Si layer. A more accurate modeling method is proposed to characterize the poly-Si and its top roughness layer using effective medium approximation (EMA) models. Using the new model, both a spectroscopic ellipsometer (SE) and a multi-angle multi-wavelength laser ellipsometer (MWLE) were employed to measure wafers with different poly-Si and gate oxide thicknesses. TEM was used to characterize the film thickness while roughness was determined using AFM. Good correlation was obtained between the TEM, AFM, and ellipsometry results. Excellent repeatability (0.04 Å 1σ on a 15 Å gate oxide for 10 days) and across the wafer uniformity (0.2 Å 1σ for a 49-point map) were also achieved when measuring gate dielectric films under the poly-Si with the MWLE.

Nitrogen Profile Engineering in Thin Gate Oxides

1998 ◽  
Vol 525 ◽  
Author(s):  
J. Kuehne ◽  
S. Hattangady ◽  
J. Piccirillo ◽  
G. C. Xing ◽  
G. Miner ◽  
...  
Keyword(s):  
Nitric Oxide ◽  
Gate Dielectrics ◽  
Depth Profiling ◽  
Gate Oxide ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Boron Penetration ◽  
Silicon Interface ◽  
Voltage Breakdown

ABSTRACTIn order to prevent boron penetration in PMOS transistors without degrading channel mobility, it is necessary to engineer the distribution of nitrogen introduced into the gate oxide. We have investigated methods of engineering this distribution using nitric oxide (NO) gas in an RTP system to thermally nitride ultra-thin gate oxides. In one approach, the gate oxide is simultaneously grown and nitrided in a mixture of nitric oxide and oxygen. For a 40 Å film, SIMS depth profiling shows that this process moves the nitrogen peak into the bulk of the oxide away from the oxide silicon interface. In another approach, an 11 Å chemical oxide produced by a standard pre-furnace wet clean is nitrided in NO at 800 deg. C. This film is subsequently reoxidized in either oxygen or steam. For an 1100 deg. C., 120 sec RTP reoxidation in oxygen, the final film thickness is 41 Å. The nitrogen has a peak concentration of 5 at. % and the peak is located in the oxide 25 Åfrom the oxide/silicon interface. Ramped voltage breakdown testing was carried out on MOS capacitors built using reoxidized NO nitrided films. They have breakdown characteristics that are equivalent to conventional furnace grown oxides. These films show considerable promise as gate dielectrics for CMOS technologies at geometries of 0.25um and below.

scholarly journals Exact statistical solution for the hopping transport of trapped charge via finite Markov jump processes

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Andrey A. Pil’nik ◽  
Andrey A. Chernov ◽  
Damir R. Islamov
Keyword(s):  
Charge Transport ◽  
Thin Layers ◽  
Jump Processes ◽  
Dielectric Films ◽  
Algebraic Equations ◽  
Markov Jump ◽  
Statistical Solution ◽  
Linear Algebraic Equations ◽  
Special Cases ◽  
Thin Dielectric Films

AbstractIn this study, we developed a discrete theory of the charge transport in thin dielectric films by trapped electrons or holes, that is applicable both for the case of countable and a large number of traps. It was shown that Shockley–Read–Hall-like transport equations, which describe the 1D transport through dielectric layers, might incorrectly describe the charge flow through ultra-thin layers with a countable number of traps, taking into account the injection from and extraction to electrodes (contacts). A comparison with other theoretical models shows a good agreement. The developed model can be applied to one-, two- and three-dimensional systems. The model, formulated in a system of linear algebraic equations, can be implemented in the computational code using different optimized libraries. We demonstrated that analytical solutions can be found for stationary cases for any trap distribution and for the dynamics of system evolution for special cases. These solutions can be used to test the code and for studying the charge transport properties of thin dielectric films.

Local range order in thin dielectric films of gallium phosphate

1996 ◽  
Vol 279 (1-2) ◽  
pp. 59-65 ◽  
Author(s):  
F. Tourtin ◽  
A. Ibanez ◽  
A. Haidoux ◽  
E. Philippot
Keyword(s):  
Range Order ◽  
Dielectric Films ◽  
Local Range ◽  
Thin Dielectric Films ◽  
Gallium Phosphate

Photovoltaic effect on the conductive atomic force microscopic characterization of thin dielectric films

2006 ◽  
Vol 89 (13) ◽  
pp. 133109 ◽  
Author(s):  
M. N. Chang ◽  
C. Y. Chen ◽  
M. J. Yang ◽  
C. H. Chien
Keyword(s):  
Photovoltaic Effect ◽  
Dielectric Films ◽  
Atomic Force ◽  
Thin Dielectric Films
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