Fine Pitch Micro-Bump Interconnections for Advanced 3D Chip Stacking

2019 ◽  
Vol 34 (1) ◽  
pp. 523-528 ◽  
Author(s):  
Wenqi Zhang ◽  
Paresh Limaye ◽  
Antonio La Manna ◽  
Eric Beyne ◽  
Philippe Soussan
Keyword(s):  
Fine Pitch ◽  
3D Chip Stacking

Scaling Challenges of Semiconductor Packaging in the Era of Big Data

2013 ◽  
Vol 2013 (1) ◽  
pp. 000402-000407 ◽  
Author(s):  
Yasumitsu Orii ◽  
Akihiro Horibe ◽  
Kazushige Toriyama ◽  
Keiji Matsumoto ◽  
Hirokazu Noma ◽  
...  
Keyword(s):  
Big Data ◽  
Material Selection ◽  
Organic Substrate ◽  
Critical Element ◽  
3D Integration ◽  
Technology Innovations ◽  
Fine Pitch ◽  
3D Chip Stacking ◽  
Semiconductor Packaging ◽  
Underfill Material

In advent of multimedia, social media and Internet of Things, our world is exploding with enormous amount of data, so-called Big Data. The use of Big Data provides us with opportunities to bring solutions and innovations to variety of industries such as healthcare, energy, banking and automotive. On the other hand, the computing requirement to analyze this large volume of data is becoming higher than ever. The exascale computing is required in the Era of Big Data. In order to achieve this demand, further technology innovations for package scaling such as 3D-IC with TSV (through silicon via) are needed. The fine pitch die-to-die interconnection is a key element in increasing the total bandwidth in 3D integration. The important technologies in 3D integration include micro-bumping, thermally enhanced underfill materials and advanced interposers. Material selection for reliable fine-pitch interconnection has become a critical challenge in 3D chip stacking. Underfill material in die-to-die device is also a critical element in reducing total packaging stress and in enhancing vertical thermal conductivity. Low CTE high-density organic substrate is an emerging technology for 2.5D structure.

Pre-Applied Underfill (PAUF) for Fine Pitch Flip Chip 3D Chip Stacking

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001432-001451
Author(s):  
Anupam Choubey ◽  
E. Anzures ◽  
A. Dhoble ◽  
D. Fleming ◽  
M. Gallagher ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Fatigue Testing ◽  
Electrical Performance ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
Semiconductor Packages ◽  
Reliability Performance ◽  
3D Chip Stacking

Current demands of the industry on performance and cost has triggered the electronics industry to use high I/O counts semiconductor packages. Copper pillar technology has been widely adopted for introducing high I/O counts in Flip Chip and 3D Chip Stacking. With the introduction of flipchip technology new avenues have been generated involving 3D chip stacking to expand the need for high performance. With the increase in the demand for high density, copper pillar technology is being adopted in the industry to address the fine pitch requirements in addition to providing enhanced thermal and electrical performance. For this study, Copper pillars and SnAg were electrolytically deposited using Dow's electroplating chemistry on internally developed test structures. After plating, wafers were diced and bonded using thermocompression bonding techniques. Copper pillar technology has been enabled to pass reliability requirements by using Underfill materials during the bonding. Underfill materials assist in redistributing the stress generated during reliability such as thermal fatigue testing. Out of the several Underfill technologies available, we have focused on pre-applied or wafer level underfill materials with 60% silica filler for this study. In the pre-applied underfill process the underfill is applied prior to bonding by coating directly on the whole wafer. Pre-applied underfill reduces the underfill dispense process time by being present prior to bonding. In this study, we have demonstrated the application of wafer level underfill for fine pitch bonding of internally developed test vehicles with SnAg-capped copper pillars with 25 μm diameter and 50 μm bump pitch. This paper demonstrates bonding alignment for fine pitch assembly with wafer level underfill to achieve 100% good solder joins after bonding. Wafer level underfill has been demonstrated successfully to bond and pass JEDEC level 3 preconditioning and standard TCT, HTS and HAST reliability tests. This paper also discusses defect mechanisms which have been found to optimize the bonding process and reliability performance. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Development of Fine Pitch Solder Microbumps for 3D Chip Stacking

2008 ◽  
Author(s):  
Aibin Yu ◽  
Aditya Kumar ◽  
Soon Wee Ho ◽  
Hnin Wai Yin ◽  
John H. Lau ◽  
...  
Keyword(s):  
Fine Pitch ◽  
3D Chip Stacking

Reballing/Rebumping Ultra-Fine Pitch Packages Less Than 0.5 mm Pitch for FA

2014 ◽  
Author(s):  
Bob Wettermann
Keyword(s):  
Solder Joint ◽  
Failure Analysis ◽  
Joint Strength ◽  
Semiconductor Devices ◽  
X Ray ◽  
Fine Pitch ◽  
Manual Methods

Abstract As the pitch and package sizes of semiconductor devices have shrunk and their complexity has increased, the manual methods by which the packages can be re-bumped or reballed for failure analysis have not kept up with this miniaturization. There are some changes in the types of reballing preforms used in these manual methods along with solder excavation techniques required for packages with pitches as fine as 0.3mm. This paper will describe the shortcomings of the previous methods, explain the newer methods and materials and demonstrate their robustness through yield, mechanical solder joint strength and x-ray analysis.

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