Reballing/Rebumping Ultra-Fine Pitch Packages Less Than 0.5 mm Pitch for FA

Author(s):  
Bob Wettermann

Abstract As the pitch and package sizes of semiconductor devices have shrunk and their complexity has increased, the manual methods by which the packages can be re-bumped or reballed for failure analysis have not kept up with this miniaturization. There are some changes in the types of reballing preforms used in these manual methods along with solder excavation techniques required for packages with pitches as fine as 0.3mm. This paper will describe the shortcomings of the previous methods, explain the newer methods and materials and demonstrate their robustness through yield, mechanical solder joint strength and x-ray analysis.

2002 ◽  
Vol 17 (1) ◽  
pp. 43-51 ◽  
Author(s):  
Won Kyoung Choi ◽  
Jong Hoon Kim ◽  
Sang Won Jeong ◽  
Hyuck Mo Lee

Interfacial phase and microstructure, solder hardness, and joint strength of Sn–3.5Ag–X (X = Cu, In, Ni; compositions are all in wt% unless specified otherwise) solder alloys were investigated. Considering the melting behavior and the mechanical properties, five compositions of Sn–3.5Ag–X solder alloys were selected. To examine the joint characteristics, they were soldered on under bump metallurgy isothermally at 250 °C for 60 s. Aging and thermal cycling (T/C) were also performed on the solder joint. The interfacial microstructure of the joint was observed by scanning electron microscopy. X-ray diffraction and energy dispersive x-ray analyses were made toidentify the type of solder phase and to measure compositions. Excessive growth of an interfacial intermetallic layer in the Sn–3.5Ag–6.5 In solder joint led to a brittle fracture. In the other four solder joints, ductile fractures occurred through the solder region and the solder hardness was closely related with the joint strength.


Author(s):  
Barbara A. Thomson ◽  
Norman J. Armendariz

Abstract A new generation X-ray laminography (XRL) automated Xray inspection (AXI) tool was evaluated for surface mount technology (SMT) assembly defect detection and was qualified using formal “benchmark” comparative analysis processes. In addition, defect characterization was performed using the XRL AXI system in manual X-ray inspection mode to correlate various failure modes and mechanisms at SMT solder joint interfaces for selected non-destructive failure analyses and technology development. Since ball grid array (BGA) solder joint quality is a great concern in board assembly, test technology development and failure analysis teams explored the use of XRL AXI as a method to detect and monitor BGA ball abnormalities using XRL AXI-generated solder ball images and measurements. It was found that XRL AXI was able to successfully discern differences in the shape, location and diameter of the suspect BGA solder balls from XRL AXI horizontal image planes (slices) for physical failure analysis and reliability issues not previously detected using conventional X-ray transmission or electrical methods. Subsequent metallographic x-sectioning correlated the XRL AXI mages to the physical condition of the suspected second level interconnect (SLI) solder joint location.


Author(s):  
Muffadal Mukadam ◽  
Michael Meilunas ◽  
K. Srihari

The purpose of this study is to evaluate three different QFP lead finishes using steam age preconditioning. This evaluation is based on solder joint strength measured by lead pull test. The effects of steam age preconditioning on solder voiding, wetting, fillet formation, and solder joint strength is included. This paper also summarizes the details of the QFP assembly build and process characterization using visual inspection, X-ray, and cross-sectional analysis. Furthermore, microscopic examination of the fracture surfaces following the lead pull tests was performed.


Author(s):  
Tomokazu Nakai

Abstract Currently many methods are available to obtain a junction profile of semiconductor devices, but the conventional methods have drawbacks, and they could be obstacles for junction profile analysis. This paper introduces an anodic wet etching-based two-dimensional junction profiling method, which is practical, efficient, and reliable for failure analysis and electrical characteristics evaluation.


Author(s):  
Y. N. Hua ◽  
Z. R. Guo ◽  
L. H. An ◽  
Shailesh Redkar

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.


Author(s):  
Carlo Grilletto ◽  
Steve Hsiung ◽  
Andrew Komrowski ◽  
John Soopikian ◽  
Daniel J.D. Sullivan ◽  
...  

Abstract This paper describes a method to "non-destructively" inspect the bump side of an assembled flip-chip test die. The method is used in conjunction with a simple metal-connecting "modified daisy chain" die and makes use of the fact that polished silicon is transparent to infra-red (IR) light. The paper describes the technique, scope of detection and examples of failure mechanisms successfully identified. It includes an example of a shorting anomaly that was not detectable with the state of the art X-ray equipment, but was detected by an IR emission microscope. The anomalies, in many cases, have shown to be the cause of failure. Once this has been accomplished, then a reasonable deprocessing plan can be instituted to proceed with the failure analysis.


Author(s):  
Charles Zhang ◽  
Matt Thayer ◽  
Lowell Herlinger ◽  
Greg Dabney ◽  
Manuel Gonzalez

Abstract A number of backside analysis techniques rely on the successful use of optical beams in performing backside fault isolation. In this paper, the authors have investigated the influence of the 1340 nm and 1064 nm laser wavelength on advanced CMOS transistor performance.


Author(s):  
Dima A. Smolyansky

Abstract The visual nature of Time Domain Reflectometry (TDR) makes it a very natural technology that can assist with fault location in BGA packages, which typically have complex interweaving layouts that make standard failure analysis techniques, such as acoustic imaging and X-ray, less effective and more difficult to utilize. This article discusses the use of TDR for package failure analysis work. It analyzes in detail the TDR impedance deconvolution algorithm as applicable to electronic packaging fault location work, focusing on the opportunities that impedance deconvolution and the resulting true impedance profile opens up for such work. The article examines the TDR measurement accuracy and the comparative package failure analysis, and presents three main considerations for package failure analysis. It also touches upon the goal and the task of the failure analysts and TDR's specific signatures for the open and short connections.


1998 ◽  
Vol 523 ◽  
Author(s):  
Hong Zhang

AbstractApplication of transmission electron microscopy on sub-half micron devices has been illustrated in terms of process evaluation and failure analysis. For process evaluation, it is emphasized that a large number of features need to be examined in order to have reliable conclusions about the processes, while for failure analysis, the goal is to pin-point a single process step causing failure or a single source introducing the particle defect.


Sign in / Sign up

Export Citation Format

Share Document