HfO2-Based Ferroelectric Field-Effect-Transistor with Large Memory Window and Good Synaptic Behavior

ABSTRACTWe report the first demonstration of an enhancement mode n-channel metal -ferroelectric-semiconductor field effect transistor (MFISFET) realized directly on silicon with yttrium oxide as the buffer layer. The capacitance-voltage (C-V) characteristics of Metal Ferroelectric Insulator Silicon (MFIS) structures show hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. The memory window in the C-V characteristics was 2V for an applied voltage of ± 10V. The memory window did not show significant change due to decrease in rate of change of sweep voltage and temperature. The transmission electron microscopy (TEM) analysis confirms the formation of an amorphous oxide layer between silicon and yttrium oxide buffer layer.

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Effect of insulator on memory window of metal-ferroelectric-insulator-semiconductor-field effect transistor (MEFISFET)-non-destructive readout memory devices

ISAF 1998. Proceedings of the Eleventh IEEE International Symposium on Applications of Ferroelectrics (Cat. No.98CH36245) ◽

10.1109/isaf.1998.786630 ◽

2002 ◽

Cited By ~ 1

Author(s):

Y.T. Kim ◽

C.W. Lee ◽

D.S. Shin ◽

H.N. Lee

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Memory Window ◽

Memory Devices ◽

Effect Transistor ◽

Non Destructive

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Electrical Characteristics of LSMCD-Derived SrBi2.4Ta2O9 Thin Films Using TiO2 Buffer Layer for Metal/Ferroelectric/Insulator/Semiconductor Field Effect Transistor Devices

MRS Proceedings ◽

10.1557/proc-623-31 ◽

2000 ◽

Vol 623 ◽

Author(s):

Joo Dong Park ◽

Tae Sung Oh

Keyword(s):

Thin Films ◽

Buffer Layer ◽

Field Effect ◽

Field Effect Transistor ◽

Chemical Deposition ◽

Memory Window ◽

Buffer Layers ◽

Liquid Source ◽

Effect Transistor ◽

Tio2 Buffer Layer

AbstractPt/SBT/TiO2/Si structure was proposed for metal/ferroelectric/insulator/semiconductor field effect transistor (MFIS-FET) applications. SrBi2.4 Ta2O9 (SBT) thin films of 400 nm thickness were prepared using liquid source misted chemical deposition (LSMCD) on Si(100) substrates with TiO2 buffer layers deposited by DC reactive sputtering with the thickness ranging from 5 nm to 200 nm and electrical properties of MFIS structures were investigated. Memory window and maximum capacitance of the Pt/SBT/TiO2 /Si structure increased with decreasing the thickness of TiO2 buffer layer. The Pt/SBT(400 nm)/TiO2(10 nm)/Si structure exhibited C-V hysteresis loop with the memory window of 1.6 V at ±5 V, and could be applicable for MFISFET applications.

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Memory window of Pt/SrBi2Ta2O9/CeO2/SiO2/Si structure for metal ferroelectric insulator semiconductor field effect transistor

Applied Physics Letters ◽

10.1063/1.120374 ◽

1997 ◽

Vol 71 (24) ◽

pp. 3507-3509 ◽

Cited By ~ 81

Author(s):

Yong Tae Kim ◽

Dong Suk Shin

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Memory Window ◽

Effect Transistor

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Memory window in ferroelectric PVDF copolymer gate integrated MOSFET devices for nondestructive readout memory application

MRS Proceedings ◽

10.1557/proc-0997-i03-02 ◽

2007 ◽

Vol 997 ◽

Author(s):

Sang-Hyun Lim ◽

Alok C Rastogi ◽

Seshu B Desu

Keyword(s):

Threshold Voltage ◽

Nonvolatile Memory ◽

Field Effect ◽

Polyvinylidene Fluoride ◽

Field Effect Transistor ◽

Memory Window ◽

Polarization Field ◽

Ferroelectric Polarization ◽

Effect Transistor ◽

Ionic Polarization

AbstractMetal-Ferroelectric-Oxide-Si (MFEOS) field effect transistor (FET) with ferroelectric polyvinylidene fluoride trifluoroethylene copolymer (PVDF-TrFE) gate for nonvolatile memory application is demonstrated. Memory window ascribed to ferroelectric polarization switching has been quantified by shift of threshold voltage are ~ 4-5V. Non saturating IDS is due to free ionic polarization field. IDS-VDS characteristics of functional FET are realized after AC poling.

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Ferroelectric transistors with asymmetric double gate for memory window exceeding 12 V and disturb-free read

Nanoscale ◽

10.1039/d1nr05107e ◽

2021 ◽

Vol 13 (38) ◽

pp. 16258-16266

Author(s):

Halid Mulaosmanovic ◽

Dominik Kleimaier ◽

Stefan Dünkel ◽

Sven Beyer ◽

Thomas Mikolajick ◽

...

Keyword(s):

Hafnium Oxide ◽

Field Effect ◽

Field Effect Transistor ◽

Memory Window ◽

Double Gate ◽

Effect Transistor ◽

Multi Level

The asymmetric double-gate hafnium oxide based ferroelectric field-effect transistor displays a memory window exceeding 12 V and multi-level storage of 4 bit per cell with a disturb-free read.

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