scholarly journals ENERGY AND POWER EFFICIENT SYSTEM ON CHIP WITH NANOSHEET FET

2019 ◽  
Vol 01 (01) ◽  
pp. 51-59 ◽  
Author(s):  
Mohan Kumar N.
Keyword(s):  
Power Dissipation ◽  
Cost Efficiency ◽  
Power Efficiency ◽  
System On Chip ◽  
Noise Tolerance ◽  
Single Chip ◽  
Efficient System ◽  
Power Efficient ◽  
On Chip ◽  
The Cost

As the level of integration of IC increases, System on Chip (SoC) design has evolved. This technology comprises of several intellectual property blocks on a single chip. With downsizing of transistors, the traditional elements used impose several challenges such as power dissipation, leakage and so on. These factors risk the cost efficiency of microsystems and risk the semiconductor industry’s capability to prolong Moore’s law in the nanometer range. This is overcome by the introduction of carbon materials such as nanosheet FET. They are advantageous over the traditional elements in terms of area and power efficiency. We design an energy and power efficient SoC with nanosheet FET that provides noise tolerance and memory optimization.

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications

2011 ◽  
Vol 30 (2) ◽  
pp. 167-179 ◽  
Author(s):  
Renshen Wang ◽  
Yulei Zhang ◽  
Nan-Chi Chou ◽  
Evangeline F. Y. Young ◽  
Chung-Kuan Cheng ◽  
...  
Keyword(s):  
System On Chip ◽  
Matrix Synthesis ◽  
Efficient System ◽  
Power Efficient ◽  
On Chip

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

2008 ◽  
Vol 57 (2) ◽  
pp. 139-153 ◽  
Author(s):  
Dragomir Milojevic ◽  
Luc Montperrus ◽  
Diederik Verkest
Keyword(s):  
Video Coding ◽  
Power Dissipation ◽  
Network On Chip ◽  
System On Chip ◽  
On Chip

Critical Issues of TSV and 3D IC Integration

2010 ◽  
Vol 7 (1) ◽  
pp. 35-43 ◽  
Author(s):  
John H. Lau
Keyword(s):  
System On Chip ◽  
The Other ◽  
Single Chip ◽  
3D Ic ◽  
Moore’S Law ◽  
Moore's Law ◽  
Other Hand ◽  
Critical Issues ◽  
Research Problems ◽  
On Chip

Moore's law has been the most powerful driver for the development of the microelectronic industry. This law is grounded in lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC). On the other hand, the integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC integration. However, there are many critical issues for 3D IC integration. In this study, some of the critical issues will be discussed and some potential solutions or research problems will be proposed.

Reliable and efficient system-on-chip design

Computer ◽  
2004 ◽  
Vol 37 (3) ◽  
pp. 42-50 ◽  
Author(s):  
N.R. Shanbhag
Keyword(s):  
System On Chip ◽  
Chip Design ◽  
Efficient System ◽  
On Chip

scholarly journals Accuracy and Physical Characterization of Approximate Arithmetic Circuits

2020 ◽  
Author(s):  
Daniela Catelan ◽  
Ricardo Santos ◽  
Liana Duenha
Keyword(s):  
Power Dissipation ◽  
Power Efficiency ◽  
Arithmetic Circuits ◽  
Approximate Computing ◽  
Accuracy Control ◽  
Field Programmable ◽  
Speed Up ◽  
Circuit Techniques ◽  
The Cost

With the end of Dennard's scale, designers have been looking for new alternatives and approximate computing (AC) has managed to attract the attention of researchers, by offering techniques ranging from the application level to the circuit level. When applying approximate circuit techniques in hardware design, the program user may speed up the application while a designer may save area and power dissipation at the cost of less accuracy on the operations results. This paper discusses the compromise between accuracy versus physical efficiency by presenting a set of experiments and results of tailor-made approximate arithmetic circuits on Field-Programmable Gate Array (FPGA) platforms. Our results reveal that an approximate circuit with accuracy control could not be useful if the goal is to save circuit area or even power dissipation. Even for circuits that seem to have power efficiency, we should care about the size and prototyping platform where the hardware will be used.

Power Efficient and Improved Noise Margin of Sram Cell for System on Chip Applications

2018 ◽  
Author(s):  
Sunil Kumar Ojha ◽  
O.P. Singh ◽  
G.R. Mishra ◽  
P.R. Vaya
Keyword(s):  
Major Part ◽  
System On Chip ◽  
Process Technology ◽  
Power Efficient ◽  
Technology Node ◽  
Noise Margin ◽  
Sram Cell ◽  
On Chip ◽  
Margin Analysis

Noise margin analysis of SRAM cell is became more crucial for on chip applications. Currently the technology is migrating towards less than 10nm node and hence it is necessary to measure the noise margin of SRAM cell very effectively, since memory is one of the major part of system on chips (SOCs) and Network on chips (NOCs) devices. If the margin is not calculated efficiently then it may leads to bad chip product and the whole device which contains this chip may not work as per the expectation. This further leads to low yield which increases the number of defective chips compared to good one. In this paper the noise margin analysis of SRAM cell is performed using 7nm process technology node using HSPICE simulator.

scholarly journals “RF-SoC”: Integration Trends of On-Chip CMOS Power Amplifier: Benefits of External PA versus Integrated PA for Portable Wireless Communications

2010 ◽  
Vol 2010 ◽  
pp. 1-7 ◽  
Author(s):  
D. Y. C. Lie
Keyword(s):  
Power Efficiency ◽  
Rf Power Amplifiers ◽  
Rf Power ◽  
Single Chip ◽  
Time To Market ◽  
Higher Power ◽  
System On A Chip ◽  
Design Tradeoffs ◽  
And Performance ◽  
On Chip

RFIC integration has seen dramatic progress since the early 1990s. For example, Si-based single-chip products for GSM, WLAN, Bluetooth, and DECT applications have become commercially available. However, RF power amplifiers (PAs) and switches tend to remain off-chip in the context of single-chip CMOS/BiCMOS transceiver ICs for handset applications. More recently, several WLAN/Bluetooth vendors have successfully integrated less demanding PAs onto the transceivers. This paper will focus on single-chip RF-system-on-a-chip (i.e., “RF-SoC”) implementations that include a high-power PA. An analysis of all tradeoffs inherent to integrating higher power PAs is provided. The analysis includes the development cost, time-to-market, power efficiency, yield, reliability, and performance issues. Recent design trends on highly integrated CMOS WiFi transceivers in the literature will be briefly reviewed with emphasis on the RF-SoC product design tradeoffs impacted by the choice between integrated versus external PAs.

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