A Novel High Speed FPGA Architecture for FIR Filter Design

2012 ◽  
Vol 1 (1) ◽  
pp. 1
Author(s):  
Sachin B. Jadhav ◽  
Nikhil Niwas Mane
Keyword(s):  
High Speed ◽  
Filter Design ◽  
Critical Path ◽  
Sampling Rate ◽  
Full Adder ◽  
Fir Filter ◽  
High Sampling ◽  
High Sampling Rate ◽  
Array Architecture ◽  
Significant Length

<em><strong> </strong></em>This paper presents the details of hardware implementation of linear phase FIR filter using merged MAC architecture. Speed of convolution operation of FIR filter is improved using merged MAC architecture. By exploiting the reduced complexity made possible by the use of sparse powers of two partial products terms coefficients, an FIR filter tap can be implemented with 2B full adders, and 2B latches, where B is intermediate wordlegnth. Word and bit level parallelism allows high sampling rates, limited only by the full adder delay. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication and accumulation operation by minimizing the number of combinational gates using higher n: 2 compressors, which is required more for Array multiplier at the time of implementation of array architecture. This novel architecture allows the implementation of high sampling rate filters of significant length on FPGA Spartan-3 device (XC3S400 PQ-208). The simulation result shows convolution output of digital FIR filter which is done using Questa Sim 6.4c Mentor Graphics tool. The experimental test of the proposed digital FIR filter is done using Spartan-3 device (XC3S400 PQ-208)

A High Speed Open-Loop Track/Hold Circuit in CMOS Process

2013 ◽  
Vol 756-759 ◽  
pp. 4302-4305
Author(s):  
Zheng Ping Zhang ◽  
Yong Lu Wang ◽  
Ming Liu
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Sampling Rate ◽  
Open Loop ◽  
Cmos Process ◽  
High Sampling ◽  
High Sampling Rate ◽  
Interleaved Structure ◽  
Offset Compensation ◽  
Loop Track

A high speed open-loop track/hold circuit in 0.18um CMOS process is presented. Open-loop and differential architecture are adopted to obtain high bandwidth and high speed;time-interleaved structure is used to reach a high sampling rate;source negative feedback and offset compensation are used to improve the linearity of the circuit.Simulation results show that with 396.875MHz input, 1.6GSPS sampling rate, driving the pre-amplifier of ADC, the thack/hold circuits SFDR(spurious-free dynamic range) is 75.8dB,satisfying the demand of 12 bits ADC.The circuit features high sampling rate,wide bandwidth,high SFDR and universal.

A Crystal View on the Design of FIR Filter

2020 ◽  
Vol 17 (9) ◽  
pp. 4235-4238
Author(s):  
R. Rohini ◽  
N. V. Satya Narayana ◽  
Durgesh Nandan
Keyword(s):  
High Speed ◽  
Critical Path ◽  
Sampling Rate ◽  
Vlsi Architecture ◽  
Complete Information ◽  
Low Complexity ◽  
Fir Filter ◽  
Main Element ◽  
Fir Filters ◽  
Hybrid Form

In audio and video signal processing main element is the FIR filter. This paper presents complete information regarding the FIR filters. It also focuses on the design of FIR filters which provide low-area, energy-delay, low-power consumption, high-speed, low critical path, and low complexity. Implementation of FIR filters with different methods like memory-based VLSI architecture, filters for sampling rate conversion, linear phase FIR filters, optimal hybrid form FIR filters, Nyquist filters, hybrid multiplier less FIR filters, low complexity FIR filters, variable partition hybrid form FIR filters, area efficiency FIR filters are discussed in this paper. The objective of this paper to provide all related information regarding FIR filters at one platform.

High Speed FIR Filter Using Radix-2r Multiplier and Its Application for Denoising EOG Signal

2021 ◽  
pp. 2150237
Author(s):  
Gundugonti Kishore Kumar ◽  
Balaji Narayanam
Keyword(s):  
High Speed ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Critical Path ◽  
Fir Filter ◽  
Path Delay ◽  
Critical Path Delay ◽  
Filter Architecture ◽  
Constant Multiplication ◽  
Fir Filter Design

In this paper, a modified finite impulse response (FIR) filter design has been proposed for the denoising bio-electrical signals like Electrooculography(EOG). The proposed filter architecture uses modified multiplier block, which is implemented using modified Radix-[Formula: see text] arithmetic-based representation for minimizing the multiple constant multiplication and conventional ripple carry adders are replaced with [Formula: see text] compressors. This proposed architecture is implemented by using Radix-[Formula: see text]-based multiplier and [Formula: see text] compressor architectures for achieving better improvement in the critical path delay. The Radix-[Formula: see text]-based arithmetic bit recording is used in order to reduce the design complexity of the multiplication. The proposed architecture significantly reduced the delay when compared to existing and conventional architectures.

scholarly journals Low Energy Less Area Less Delay Fixed Point LMS Method for Adaptive Noise Cancellation Filter

2020 ◽  
Vol 8 (6S) ◽  
pp. 195-203
Keyword(s):  
Adaptive Filtering ◽  
High Speed ◽  
Critical Path ◽  
Sampling Rate ◽  
Low Complexity ◽  
Least Mean Square ◽  
High Sampling Rate ◽  
Low Complexity Implementation ◽  
Lms Method ◽  
Adaptive Noise

Present paper is about the high speed low complexity implementation derived by its architecture using least mean square (LMS) adaptive filtering. Here straight form LMS adaptive filter has almost the similar critical path as it is a reverse from of the counter path hoiver it has a fast coverage and also a loir register complication. Here critical path evaluation tells that no pipelining is necessary for implementation of straight form LMS adaptive filtering in most of the practical cases requires a realized extremely small adaptive delay and very high sampling rate. Here based on these finding LMS adaptive filtering is divided into 3 structural proposal designs. a) There is no adaption delay b) Only one adaption delay c) Only two adaption delay. Here first one includes least area and least energy per sample (EPS).

All-optical parallelization for high sampling rate photonic ADC in fully digital radar systems

2010 ◽  
Author(s):  
Paolo Ghelfi ◽  
Lingmei Ma ◽  
Xiaoxia Wu ◽  
Minyu Yao ◽  
Alan E. Willner ◽  
...  
Keyword(s):  
Sampling Rate ◽  
Radar Systems ◽  
High Sampling ◽  
High Sampling Rate ◽  
All Optical

scholarly journals High sampling rate thermistor string observations at the slope of Great Meteor Seamount

Ocean Science ◽  
2005 ◽  
Vol 1 (1) ◽  
pp. 17-28 ◽  
Author(s):  
H. van Haren ◽  
R. Groenewegen ◽  
M. Laan ◽  
B. Koster
Keyword(s):  
High Frequency ◽  
North Atlantic Ocean ◽  
Sampling Rate ◽  
Very High Frequency ◽  
High Sampling ◽  
High Sampling Rate ◽  
In Situ Calibration ◽  
Great Meteor Seamount ◽  
Very High

Abstract. A high sampling rate (1 Hz) thermistor string has been built to accommodate the scientific need to accurately monitor high-frequency and vigorous internal wave and overturning processes in the ocean. The thermistors and their custom designed electronics can register temperature at an estimated precision of about 0.001° C with a response time faster than 0.25 s down to depths of 6000 m. With a quick in situ calibration using SBE 911 CTD an absolute accuracy of 0.005° C is obtained. The present string holds 128 sensors at 0.5 m intervals, which are all read-out within 0.5 s. When sampling at 1 Hz, the batteries and the memory capacity of the recorder allow for deployments of up to 2 weeks. In this paper, the instrument is described in some detail. Its performance is illustrated with examples from the first moored observations, which show Kelvin-Helmholtz overturning and very high-frequency (Doppler-shifted) internal waves besides occasionally large turbulent bores moving up the sloping side of Great Meteor Seamount, Canary Basin, North-Atlantic Ocean.

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

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