We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 μm SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.
An experimental sample of a 12-bit digital-to-analog converter with high linearity has been developed. Segmentation and the use of binary-weighted switches were used to improve the values of integral and differential nonlinearities.
The formulated optimal requirements sectional bezkontaktni DAC. Considered are the main technological and frequency limitations sovovych DAC with low power consumption. Suggested 4-bit binary-weighted Zogby differential DAC architecture analogue circuit.
Settling time optimization technique for binary-weighted digital-to-analog converter
