scholarly journals Symmetric stacked fast binary counters based on reversible logic

2018 ◽  
Vol 7 (4) ◽  
pp. 2747
Author(s):  
C Santhi ◽  
Dr. Moparthy Gurunadha Babu
Keyword(s):  
Energy Dissipation ◽  
Circuit Design ◽  
Power Dissipation ◽  
Heat Dissipation ◽  
Logic Gates ◽  
Digital Circuit ◽  
Information Loss ◽  
Reversible Logic ◽  
Binary Counter ◽  
Reversible Logic Gates

A Symmetric Stacked Fast Binary counter design is proposed in this paper. In the circuit design, the first phase is occupied by 3-bit stacking circuits, which are further followed by combining circuits. The resultant novel circuit thus becomes a 6-bit stacker. A 6:3 counter has been chosen as an example to demonstrate the working of the proposed circuit. The proposed circuit is further implemented by using reversible logic gates. Heat dissipation is a major problem in the designing of a digital circuit. Rolf Landauer has proved that the information loss in a digital circuit is directly proportional to the energy dissipation. The proposed modified Symmetric Stacking counter is implemented using reversible logic gates thus reducing the power dissipation of the circuit. 

scholarly journals Energy dissipation dataset for reversible logic gates in quantum dot-cellular automata

Data in Brief ◽  
2017 ◽  
Vol 10 ◽  
pp. 557-560 ◽  
Author(s):  
Ali Newaz Bahar ◽  
Mohammad Maksudur Rahman ◽  
Nur Mohammad Nahid ◽  
Md. Kamrul Hassan
Keyword(s):  
Energy Dissipation ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Logic Gates ◽  
Reversible Logic ◽  
Quantum Dot Cellular Automata ◽  
Reversible Logic Gates

Estimation of Power for Reversible Subtractors

2018 ◽  
Vol 7 (4.5) ◽  
pp. 102
Author(s):  
E. V.Naga Lakshmi ◽  
Dr. N.Siva Sankara Reddy
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Garbage Output ◽  
Reversible Logic Gates

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG).   Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor.  Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.  

scholarly journals High functionality reversible arithmetic logic unit

2020 ◽  
Vol 10 (3) ◽  
pp. 2329
Author(s):  
Shaveta Thakral ◽  
Dipali Bansal
Keyword(s):  
Power Dissipation ◽  
Logic Gates ◽  
Reversible Logic ◽  
Logic Design ◽  
Quantum Cost ◽  
Verilog Hdl ◽  
Power Efficient ◽  
Reversible Logic Gates ◽  
Reversible Alu ◽  
Logic Unit

Energy loss is a big challenge in digital logic design primarily due to impending end of Moore’s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17 % reduction in garbage lines, 92 % reduction in ancillary lines and 53 % reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design.

scholarly journals Implementation of Low Power Carry Skip Adder using Reversible Logic

2019 ◽  
Vol 8 (3) ◽  
pp. 2825-2832
Keyword(s):  
Arithmetic Operation ◽  
Logic Gates ◽  
Full Adder ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Basic Block ◽  
Arithmetic Unit ◽  
Input And Output ◽  
The One ◽  
Reversible Logic Gates

Addition is a vital arithmetic operation. It is the base of commonly used arithmetic operations such as division, subtraction, and multiplication. Adder is a digital circuit that accomplishes addition of numbers. The one bit full adder is the basic block of an arithmetic unit. There are several adder designs implemented so far to reduce the power. However, each design suffers from exact drawback. Reversible logic is the growing technology in the current era. The numbers of input and output lines in reversible logic are equal. In reversible logic the inputs are to be recovered from the outputs. Reversible logic gates are defined by the user. In this paper Carry Skip Adder (CSKA) is implemented in two different designs i.e. design-I and design-II. Design-I is implemented using Peres gates with irreversible (XOR, AND, OR) logic gates. Design-II is implemented using PERES, TOFFOLI, and FREDKIN reversible logic gates. Design-I and design-II designs are synthesized and simulated by Mentor Graphics tool. Design-II is more efficient in terms of transistor count and power consumption compared to DesignI.

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