The Quantum Cost Optimized Design of 2:4 Decoder Using the New Reversible Logic Block

Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.

Design of Quantum Cost and Delay Optimized Code Converter Using New Reversible Quantum Circuit Block (QCB)

Background: In this article, we have proposed a new reversible quantum circuit block along with the quantum cost (QC), constant input (CI), garbage output (GO) and delay optimized code converterusing quantum circuit block. Method: Initially, new quantum circuit block has been designed and later reversible code converter circuits have been implemented using it. The proposed new quantum blockused to design 2’s complement code converter (2SCCC), cost efficient BCD to Excess-3 code converter (BECC) and can also be used to implement different logic functions. The QC of proposed quantum circuit block is 8. The QC and delay of the proposed 2SCCC is 8 and 1 respectively. Similarly, the QC and delay of the proposed BECC is 11 and 2 respectively. The proposed cost efficient BECC is designed using two NOT gate, one Feynman gate and one new quantum circuit block with QC is 11. Results: The improvement of QC for 2SCCC and BECC are 27.27 % and 21.43% respectively. The improvement of delay for 2SCCC and BECC are 66.67% and 50% respectively compared with respect to the latest reported results. Conclusion: So the improvement of QC and delay are very high using QCB.

Realization and Optimization of Quantum Equivalent Circuits of Reversible Combinational Circuits

Energy dissipation is the important constrain in the design and implementation of VLSI circuits. Usage of Reversible logic circuit is the best solution for lower energy dissipation. In this paper, basic reversible gates and some existing gates and KMD gates are realized using the Quantum Equivalent structure and the Controlled-V and V+ gate structure from their functional expression. Using the qubit gate reduction procedure of quantum circuit, the quantum cost and number of primitive gates of the functional expression are deduced. After synthesizing the Quantum Cost (QC), Gate count (GC), Garbage Output (GO), number of gates, constant inputs are compared with the non-optimized circuit. The quantum circuit and controlled V and V+ structure are realized in RCViewer+ tool using .tfc (“Toffoli-Fredkin Cascade”) code.

ALL OPTICAL REVERSIBLE DATA DISTRIBUTOR

Nowadays, It became the fashion among the researchers about creating the New Reversible Gates. In the Reversible Literature, already many gates are proposed but it is the first time to propose a Gate for a decoder(Data Distributor). The proposed GLG (Garbage Less Gate) has No Garbage output which denotes its power efficiency. In this paper 2:4 reversible decoder is constructed using GLG. The proposed gate is also extended to N:2N decoder using the proposed GLG Gate and the Fredkin Gate. The theoretical proposition is verified through Optisystem & Modelsim Software. A comparison with existing reversible decoders is also included.

Design of quaternary quantum reversible half subtractor, full subtractor and n-qudit borrow ripple subtractor

In this paper, we proposed novel plans of quaternary quantum reversible half and full subtractor circuits. The subtractor element is the essential part of the ALU in the digital computational devices. Thus, the improvement of subtractor block has a significant impact on the overall system performance. According to the comparison results, the proposed quaternary quantum half and full subtractor circuits show tremendous improvement in quantum cost, hardware complexity, number of constant input and garbage output as compared to their counterparts. Moreover, for the first time, the quaternary quantum borrow ripple subtractor structure is realized using the proposed quaternary quantum half and full subtractor circuits.

Design of BCD to Excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate

In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible logic gate. BCD to Excess-3 code can be generated by adding “0011” to BCD number, but in the proposed work, addition is not required. The proposed reversible circuit can be designed using peres gate, Feynman gate and NOT gate optimized quantum cost, garbage output and constant input. The quantum cost (QC), garbage output and constant input of proposed reversible BCD to Excess-3 code converter are respectively 14, 1 and 1 which is better with respect to previously reported results. The improvement is, respectively 0–65%, 66.66–91.66% and 66.66–87.5%.

Estimation of Power for Reversible Subtractors

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG). Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor. Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.

Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.