scholarly journals Time interval measurement module implemented in SoC FPGA device

2016 ◽  
Vol 62 (3) ◽  
pp. 237-246 ◽  
Author(s):  
Grzegorz Grzęda ◽  
Ryszard Szplet

Abstract We presents the design and test results of a picosecond-precision time interval measurement module, integrated as a System-on-Chip in an FPGA device. Implementing a complete measurement instrument of a high precision in one chip with the processing unit gives an opportunity to cut down the size of the final product and to lower its cost. Such approach challenges the constructor with several design issues, like reduction of voltage noise, propagating through power lines common for the instrument and processing unit, or establishing buses efficient enough to transport mass measurement data. The general concept of the system, design hierarchy, detailed hardware and software solutions are presented in this article. Also, system test results are depicted with comparison to traditional ways of building a measurement instrument.


Measurement ◽  
1997 ◽  
Vol 22 (3-4) ◽  
pp. 129-140 ◽  
Author(s):  
Domenico Mirri ◽  
Gaetano Pasini ◽  
Gaetano Iuculano ◽  
Fabio Filicori ◽  
Gabriella Pellegrini ◽  
...  


ACTA IMEKO ◽  
2015 ◽  
Vol 4 (1) ◽  
pp. 77
Author(s):  
Marek Zielinski ◽  
Maciej Gurski ◽  
Dariusz Chaberski

This paper describes the architecture of a Multi-Tap-Delay-Line (MTDL) time-interval measurement module of high resolution implemented in a single FPGA device. The new architecture of the measurement module enables to collect sixteen time-stamps during a single measuring cycle. It means that the measured time-interval can be precisely interpolated from the collection of the sixteen time-stamps after each measuring cycle. Such architecture of the measurement module leads directly to an increased resolution, to a limited total measurement time and a decreased duty cycle of the measurement instrument.





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