2.5 Gbit/s Optical Receiver Front-End Circuit with High Sensitivity and Wide Dynamic Range

2017 ◽  
Vol 38 (4) ◽  
Author(s):  
Tiezhu Zhu ◽  
Taishan Mo ◽  
Tianchun Ye

AbstractAn optical receiver front-end circuit is designed for passive optical network and fabricated in a 0.18 um CMOS technology. The whole circuit consists of a transimpedance amplifier (TIA), a single-ended to differential amplifier and an output driver. The TIA employs a cascode stage as the input stage and auxiliary amplifier to reduce the miller effect. Current injecting technique is employed to enlarge the input transistor’s transconductance, optimize the noise performance and overcome the lack of voltage headroom. To achieve a wide dynamic range, an automatic gain control circuit with self-adaptive function is proposed. Experiment results show an optical sensitivity of –28 dBm for a bit error rate of 10

2002 ◽  
Vol 38 (13) ◽  
pp. 650 ◽  
Author(s):  
H. Matsuda ◽  
A. Miura ◽  
H. Irie ◽  
S. Tanaka ◽  
K. Ito ◽  
...  

Sensors ◽  
2019 ◽  
Vol 19 (3) ◽  
pp. 512
Author(s):  
Binghui Lin ◽  
Mohamed Atef ◽  
Guoxing Wang

A low-power, high-gain, and low-noise analog front-end (AFE) for wearable photoplethysmography (PPG) acquisition systems is designed and fabricated in a 0.35 μm CMOS process. A high transimpedance gain of 142 dBΩ and a low input-referred noise of only 64.2 pArms was achieved. A Sub-Hz filter was integrated using a pseudo resistor, resulting in a small silicon area. To mitigate the saturation problem caused by background light (BGL), a BGL cancellation loop and a new simple automatic gain control block are used to enhance the dynamic range and improve the linearity of the AFE. The measurement results show that a DC photocurrent component up-to-10 μA can be rejected and the PPG output swing can reach 1.42 Vpp at THD < 1%. The chip consumes a total power of 14.85 μW using a single 3.3-V power supply. In this work, the small area and efficiently integrated blocks were used to implement the PPG AFE and the silicon area is minimized to 0.8 mm × 0.8 mm.


1996 ◽  
Vol 8 (9) ◽  
pp. 1232-1234 ◽  
Author(s):  
T.Y. Yun ◽  
M.S. Park ◽  
J.H. Han ◽  
I. Watanabe ◽  
K. Makita

2015 ◽  
Vol 719-720 ◽  
pp. 548-553
Author(s):  
Feng Guo ◽  
Shan Shan Yong ◽  
Zhao Yang Guo ◽  
Xin An Wang ◽  
Guo Xin Zhang

In this paper, a new design strategy for the hardware implementation of hearing aid algorithms is proposed. Two familiar hearing aid algorithms—Wide Dynamic Range Compression (WDRC) and Automatic Gain Control (AGC)—are implemented in one circuit as an example. By putting the common arithmetic procedures into common module, the operation units can be used repeatedly. In this way, the area and power consumption are visibly reduced.


2013 ◽  
Vol 142 ◽  
pp. 261-273
Author(s):  
Bo Zhang ◽  
Yong-Zhong Xiong ◽  
Lei Wang ◽  
Sanming Hu ◽  
Joshua Le-Wei Li

2003 ◽  
Vol 39 (1) ◽  
pp. 91 ◽  
Author(s):  
R. Vetury ◽  
I. Gontijo ◽  
Yet-zen Liu ◽  
K. Krishnamurthy ◽  
R. Pullela ◽  
...  

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