Cosmic-Ray Neutrons on the Ground and in the Atmosphere

MRS Bulletin ◽  
2003 ◽  
Vol 28 (2) ◽  
pp. 131-135 ◽  
Author(s):  
Paul Goldhagen
Keyword(s):  
Cosmic Rays ◽  
State Of The Art ◽  
Cosmic Ray ◽  
Error Rates ◽  
Soft Error ◽  
Single Event ◽  
External Radiation ◽  
Neutron Spectra ◽  
Single Event Upsets ◽  
Microelectronic Devices

AbstractNeutrons from collisions of cosmic rays with the nuclei of atoms in the atmosphere are an irremovable external radiation that causes single-event upsets in microelectronic devices. Predicting soft error rates requires knowledge of the flux and energy distribution of the cosmic-ray-induced neutrons. This article reviews cosmic-ray neutrons in the atmosphere and on the ground, the factors that determine their intensity, and recent calculations and state-of-the-art measurements of neutron spectra covering 12 decades of energy, from the thermal energy range up to 10 GeV.

Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations

2014 ◽  
Vol 24 (01) ◽  
pp. 1550007 ◽  
Author(s):  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Mahdi Fazeli
Keyword(s):  
Propagation Delay ◽  
Soft Error ◽  
The Other ◽  
Design Parameters ◽  
Single Event ◽  
Temperature Variations ◽  
Single Event Upsets ◽  
Radiation Hardened ◽  
Simulation Results ◽  
Power Delay Product

In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability of enduring single event multiple upsets (SEMUs). Our simulation results show that, both of our HRPU and HRUT latches have higher robustness against SEMUs as compared with other recently proposed radiation hardened latches. We have also explored the effects of process and temperature variations on different design parameters such as delay and power consumption of our proposed latches and other leading SEU tolerant latches. Our simulation results also show that, compared with the reference (unprotected) latch, our HRPU latch has 57% and 34% improvements in propagation delay and power delay product (PDP) respectively. In addition, process and temperature variations have least effects on HRPU in comparison with the other latches. Allowing little more delay, we designed HRUT latch that can filter single event transients (SETs). HRUT has been designed to be immune against SEUs, SEMUs and SETs with an acceptable overhead and sensitivity to process and temperature variations.

Single-Event Upsets in Microelectronics: Fundamental Physics and Issues

MRS Bulletin ◽  
2003 ◽  
Vol 28 (2) ◽  
pp. 111-116 ◽  
Author(s):  
Henry H.K. Tang ◽  
Kenneth P. Rodbell
Keyword(s):  
Cosmic Rays ◽  
Cross Sections ◽  
Background Radiation ◽  
Complementary Metal Oxide Semiconductor ◽  
Alpha Particles ◽  
Oxide Semiconductor ◽  
Thermal Neutrons ◽  
Single Event ◽  
Single Event Upsets ◽  
Future Technologies

AbstractWe review the current understanding of single-event upsets (SEUs) in microelectronic devices. In recent years, SEUs have been recognized as one of the key reliability concerns for both current and future technologies. We identify the major sources of SEUs that impact many commercial products: (1) alpha particles in packaging materials, (2) background radiation due to cosmic rays, and (3) thermal neutrons in certain device materials. The origins of SEUs are examined from the standpoint of the fundamental atomic and nuclear interactions between the intruding particles (alpha particles, cosmic rays, and thermal neutrons) and semiconductor materials. We analyze field funneling, which is a key mechanism of charge collection in a device struck by an ionizing particle. Next, we formulate how SEU cross sections and SEU rates are calculated and discuss how these basic quantities are related to experiments. Finally, we summarize the major SEU issues regarding modeling, bulk complementary metal oxide semiconductor technologies, and research on future, exploratory technologies.

Single event upsets of spacecraft microelectronics exposed to solar cosmic rays

1996 ◽  
Vol 26 (6) ◽  
pp. 959-965 ◽  
Author(s):  
N.V. Kuznetsov ◽  
R.A. Nymmik
Keyword(s):  
Cosmic Rays ◽  
Single Event ◽  
Solar Cosmic Rays ◽  
Single Event Upsets

Impact of Single-Event Upsets in Deep-Submicron Silicon Technology

MRS Bulletin ◽  
2003 ◽  
Vol 28 (2) ◽  
pp. 117-120 ◽  
Author(s):  
Robert Baumann
Keyword(s):  
Soft Errors ◽  
Deep Submicron ◽  
Soft Error ◽  
Mitigation Strategies ◽  
Single Event ◽  
Radiation Mechanisms ◽  
Silicon Technology ◽  
Single Event Upsets ◽  
Radiation Induced ◽  
Considerable Concern

AbstractThe once-ephemeral soft error phenomenon has recently caused considerable concern for manufacturers of advanced silicon technology. Soft errors, if unchecked, now have the potential for inducing a higher failure rate than all of the other reliability-failure mechanisms combined. This article briefly reviews the three dominant radiation mechanisms responsible for soft errors in terrestrial applications and how soft errors are generated by the collection of radiation-induced charge. Scaling trends in the soft error sensitivity of various memory and logic components are presented, along with a consideration of which applications are most likely to require intervention. Some of the mitigation strategies that can be employed to reduce the soft error rate in these devices are also discussed.

scholarly journals ULTRAHIGH ENERGY COSMIC RAYS: THE STATE OF THE ART BEFORE THE AUGER OBSERVATORY

2003 ◽  
Vol 18 (13) ◽  
pp. 2229-2366 ◽  
Author(s):  
LUIS ANCHORDOQUI ◽  
THOMAS PAUL ◽  
STEPHEN REUCROFT ◽  
JOHN SWAIN
Keyword(s):  
Cosmic Rays ◽  
State Of The Art ◽  
Cosmic Ray ◽  
Mass Composition ◽  
Beyond The Standard Model ◽  
Ultrahigh Energy ◽  
The Standard Model ◽  
Physical Laws ◽  
Important Progress ◽  
Made In

In this review we discuss the important progress made in recent years towards understanding the experimental data on cosmic rays with energies ≳ 1019eV. We begin with a brief survey of the available data, including a description of the energy spectrum, mass composition, and arrival directions. At this point we also give a short overview of experimental techniques. After that, we introduce the fundamentals of acceleration and propagation in order to discuss the conjectured nearby cosmic ray sources. We then turn to theoretical notions of physics beyond the Standard Model where we consider both exotic primaries and exotic physical laws. Particular attention is given to the role that TeV-scale gravity could play in addressing the origin of the highest energy cosmic rays. In the final part of the review we discuss the potential of future cosmic ray experiments for the discovery of tiny black holes that should be produced in the earth's atmosphere if TeV-scale gravity is realized in Nature.

SEU-SECURE PARITY PREDICTION MULTIPLIER ON SRAM-BASED FPGAs

2014 ◽  
Vol 23 (06) ◽  
pp. 1450081 ◽  
Author(s):  
REZA OMIDI GOSHEBLAGH ◽  
KARIM MOHAMMADI
Keyword(s):  
Field Programmable Gate Array ◽  
Fault Injection ◽  
Soft Error ◽  
Space Systems ◽  
Single Event ◽  
Single Event Upsets ◽  
Average Area ◽  
Error Mitigation ◽  
Field Programmable ◽  
Mitigation Techniques

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing satellites and space systems. Unfortunately, these devices are extremely sensitive to various kinds of unwanted effects induced by space radiations especially single-event upsets (SEUs) as soft errors in configuration memory. To face this challenge, a variety of soft error mitigation techniques have been adopted in literature. In this paper, we describe an area-efficient multiplier architecture based on SRAM-FPGA that provides the self-checking capability against SEU faults. The proposed design approach, which is based on parity prediction, is able to concurrently detect the SEU faults. The implementation results of the proposed architecture reveal that the average area and delay overheads are respectively 25% and 34% in comparison with the plain version while the conventional duplication with comparison (DWC) architecture imposes 117% and 22% overheads. Moreover, the single and multi-upset fault injection experiments reveal that the proposed architecture averagely provides the failure coverage of 83% and 79% while the failure coverage of the duplicated structure is 85% and 84%, respectively for SEU and MEU faults.

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