Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations

2014 ◽  
Vol 24 (01) ◽  
pp. 1550007 ◽  
Author(s):  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Mahdi Fazeli
Keyword(s):  
Propagation Delay ◽  
Soft Error ◽  
The Other ◽  
Design Parameters ◽  
Single Event ◽  
Temperature Variations ◽  
Single Event Upsets ◽  
Radiation Hardened ◽  
Simulation Results ◽  
Power Delay Product

In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability of enduring single event multiple upsets (SEMUs). Our simulation results show that, both of our HRPU and HRUT latches have higher robustness against SEMUs as compared with other recently proposed radiation hardened latches. We have also explored the effects of process and temperature variations on different design parameters such as delay and power consumption of our proposed latches and other leading SEU tolerant latches. Our simulation results also show that, compared with the reference (unprotected) latch, our HRPU latch has 57% and 34% improvements in propagation delay and power delay product (PDP) respectively. In addition, process and temperature variations have least effects on HRPU in comparison with the other latches. Allowing little more delay, we designed HRUT latch that can filter single event transients (SETs). HRUT has been designed to be immune against SEUs, SEMUs and SETs with an acceptable overhead and sensitivity to process and temperature variations.

scholarly journals Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1572
Author(s):  
Ehab A. Hamed ◽  
Inhee Lee
Keyword(s):  
Soft Error ◽  
Error Tolerance ◽  
Cmos Process ◽  
Flip Flop ◽  
Single Event Upsets ◽  
Area Overhead ◽  
Fair Comparison ◽  
Reference Design ◽  
Radiation Hardened ◽  
Radiation Hardened By Design

In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.

scholarly journals Single-Event Upsets and Distributions in Radiation-Hardened CMOS Flip-Flop Logic Chains

2011 ◽  
Vol 58 (6) ◽  
pp. 2695-2701 ◽  
Author(s):  
Paul E. Dodd ◽  
Marty R. Shaneyfelt ◽  
Richard S. Flores ◽  
James R. Schwank ◽  
Thomas A. Hill ◽  
...  
Keyword(s):  
Single Event ◽  
Flip Flop ◽  
Single Event Upsets ◽  
Radiation Hardened

Soft Error-Resilient RHBD16T SRAM Cell in 32nm Technology

2021 ◽  
pp. 171-188
Author(s):  
Gaurav Kaushal ◽  
Balamurugan Murgan ◽  
Manisha Pattanaik ◽  
Chinnapurapu Naga Raghuram ◽  
Surendra Singh Rathod
Keyword(s):  
Random Access ◽  
Error Rates ◽  
Soft Error ◽  
Radiation Environment ◽  
Static Random Access Memory ◽  
Single Node ◽  
Error Resilient ◽  
Sram Cell ◽  
Radiation Hardened ◽  
Simulation Results

Radiation environment generates high soft error rates in conventional SRAM. To overcome this issue, several radiation hardened by design SRAM circuits (12TRHBD, 13TRHBD, DICE, etc.) have been developed. Although many of the radiation hardened SRAM cells are there, all the circuits mainly concern a single node upset only. In this chapter, 16T radiation hardened static random-access memory bit cell is designed and verified for a single node and multi-node upset. RHBD 16T bit cell is designed with SAED-PDK 32nm technology and compared with recently reported RHBD 12T and has a 99% improvement in recovery rate. Simulation results show that RHBD 16T is more resilient to a single node and multi-node upset. This shows that the proposed RHBD16T cell is highly tolerant against radiation strikes.

Impact of Single-Event Upsets in Deep-Submicron Silicon Technology

MRS Bulletin ◽  
2003 ◽  
Vol 28 (2) ◽  
pp. 117-120 ◽  
Author(s):  
Robert Baumann
Keyword(s):  
Soft Errors ◽  
Deep Submicron ◽  
Soft Error ◽  
Mitigation Strategies ◽  
Single Event ◽  
Radiation Mechanisms ◽  
Silicon Technology ◽  
Single Event Upsets ◽  
Radiation Induced ◽  
Considerable Concern

AbstractThe once-ephemeral soft error phenomenon has recently caused considerable concern for manufacturers of advanced silicon technology. Soft errors, if unchecked, now have the potential for inducing a higher failure rate than all of the other reliability-failure mechanisms combined. This article briefly reviews the three dominant radiation mechanisms responsible for soft errors in terrestrial applications and how soft errors are generated by the collection of radiation-induced charge. Scaling trends in the soft error sensitivity of various memory and logic components are presented, along with a consideration of which applications are most likely to require intervention. Some of the mitigation strategies that can be employed to reduce the soft error rate in these devices are also discussed.

scholarly journals Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1256
Author(s):  
Seyedehsomayeh Hatefinasab ◽  
Noel Rodriguez ◽  
Antonio García ◽  
Encarnacion Castillo
Keyword(s):  
Standard Deviation ◽  
Power Consumption ◽  
Threshold Voltage ◽  
Low Cost ◽  
Process Variations ◽  
Cmos Technology ◽  
Soft Error ◽  
Single Event ◽  
Power Delay Product ◽  
The Impact

In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.

SEU-SECURE PARITY PREDICTION MULTIPLIER ON SRAM-BASED FPGAs

2014 ◽  
Vol 23 (06) ◽  
pp. 1450081 ◽  
Author(s):  
REZA OMIDI GOSHEBLAGH ◽  
KARIM MOHAMMADI
Keyword(s):  
Field Programmable Gate Array ◽  
Fault Injection ◽  
Soft Error ◽  
Space Systems ◽  
Single Event ◽  
Single Event Upsets ◽  
Average Area ◽  
Error Mitigation ◽  
Field Programmable ◽  
Mitigation Techniques

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing satellites and space systems. Unfortunately, these devices are extremely sensitive to various kinds of unwanted effects induced by space radiations especially single-event upsets (SEUs) as soft errors in configuration memory. To face this challenge, a variety of soft error mitigation techniques have been adopted in literature. In this paper, we describe an area-efficient multiplier architecture based on SRAM-FPGA that provides the self-checking capability against SEU faults. The proposed design approach, which is based on parity prediction, is able to concurrently detect the SEU faults. The implementation results of the proposed architecture reveal that the average area and delay overheads are respectively 25% and 34% in comparison with the plain version while the conventional duplication with comparison (DWC) architecture imposes 117% and 22% overheads. Moreover, the single and multi-upset fault injection experiments reveal that the proposed architecture averagely provides the failure coverage of 83% and 79% while the failure coverage of the duplicated structure is 85% and 84%, respectively for SEU and MEU faults.

scholarly journals Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-13 ◽  
Author(s):  
Joyjit Mukhopadhyay ◽  
Soumya Pandit
Keyword(s):  
Good Accuracy ◽  
Particle Swarm Optimization Algorithm ◽  
Propagation Delay ◽  
Design Parameters ◽  
Process Technology ◽  
Cmos Inverter ◽  
Swarm Optimization ◽  
Nano Scale ◽  
Simulation Results ◽  
Switching Characteristics

This paper presents a technique for the modeling and design of a nano scale CMOS inverter circuit using artificial neural network and particle swarm optimization algorithm such that the switching characteristics of the circuit is symmetric, that is, has nearly equal rise and fall time and equal output high-to-low and low-to-high propagation delay. The channel width of the transistors and the load capacitor value are taken as design parameters. The designed circuit has been implemented at the transistor-level and simulated using TSPICE for 45 nm process technology. The PSO-generated results have been compared with SPICE results. A very good accuracy has been achieved. In addition, the advantage of the present approach over an existing approach for the same purpose has been demonstrated through simulation results.

scholarly journals LIHL: Design of a Novel Loop Interlocked Hardened Latch

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2090
Author(s):  
Hui Xu ◽  
Xuan Liu ◽  
Guo Yu ◽  
Huaguo Liang ◽  
Zhengfeng Huang
Keyword(s):  
Power Dissipation ◽  
High Reliability ◽  
Complementary Metal Oxide Semiconductor ◽  
Propagation Delay ◽  
Metal Oxide Semiconductor ◽  
Soft Error ◽  
Oxide Semiconductor ◽  
Low Power Consumption ◽  
Single Event ◽  
Single Event Transient

A single event causing a double-node upset is likely to occur in nanometric complementary metal-oxide-semiconductor (CMOS). Contemporary hardened latch designs are insufficient in meeting high reliability, low power consumption, and low delay. This paper presents a novel soft error hardened latch, known as a loop interlocked hardened latch (LIHL). This latch consists of four modified cross-coupled elements, based on dual interlocked storage cell (DICE) latch. The use of these elements hardens the proposed LIHL to soft errors. The simulation results showed that the LIHL has single-event double upset (SEDU) self-recoverability and single-event transient (SET) pulse filterability. This latch also reduces power dissipation and propagation delay, compared to other SEDU or SET-tolerant latches.

Sign in / Sign up

Export Citation Format

Share Document